Masato Kitakami

Prolongation of Lifetime and the Evaluation Method of Dependable SSD

Since high-density flash memory has high error rate, strong error control is necessary for the solid-state drive (SSD). The number of erasure cycles of each memory cell is limited, where the cell should be erased before writing. Wear-leveling is used for leveling the erasure cycles in a flash memory. Since the existing wear-leveling is executed in a chip, it is not effective if write operations are concentrated into specified chips. This paper proposes wear-leveling and error control method by using redundant flash memories in order to improve reliability and lifetime of the SSD. In the proposed method, error control is usually executed, and wear-leveling among the chips is executed when the bias in the erasure cycles is large. The execution frequency of wear-leveling is adjusted considering deterioration of the cell. Evaluations of bit error rate and lifetime show that the proposed method has high reliability and durability.

A class of error-locating codes for byte-organized memory systems

Error-locating codes (EL codes), first proposed by J.K. Wolf and B. Elspas in 1963, have the potential to be used to identify the faulty module for fault isolation and reconfiguration in fault-tolerant computer systems. This paper proposes a new class of EL codes suitable for memory systems organized with b-bit (b/spl ges/2) byte-organized semiconductor memory chips that are mounted on memory cards each having B-bit width. The proposed linear code, called the S/sub b/B/EL code, identifies erroneous memory card locations containing a faulty byte-organized chip. Another linear code proposed in this paper, the SEC-S/sub b/B/EL code, corrects single-bit errors induced by alpha particles and, for byte errors, it locates erroneous card positions containing a faulty chip. This paper describes design methods of the proposed codes and shows an evaluation of the decoding hardware and the error detection capabilities. >

Optimal two-level unequal error control codes for computer systems

Error control codes are now successfully applied to computer systems and communication systems. When we consider some types of computer words or communication messages, the information in some part of the word is more important than the other. Address and control information in computer words and communication messages and pointer information in database words are good examples. The more important the part of the word is, or the less reliable the part is, the more strongly it should be protected from errors. Based on this, this paper proposes a new class of codes, called unequal error control codes, which have some unequal error control levels in the codeword, that is, have some distinct code functions in the codeword and protect the part of the word from errors according to its importance or reliability level. From a simple and practical viewpoint, this paper adopts the model of the codeword which includes two unequal levels: one having strong error control level in some part of the codeword, called fixed-byte, and the other having relatively weak error control level outside the fixed-byte. This paper deals with three basic unequal error control codes. For all types of codes, the paper clarifies necessary and sufficient conditions and bounds on code length and demonstrates code construction method of the optimal codes and evaluation of these codes from the perspectives of error correction/detection capability and decoder hardware complexity.

Reliable logic circuits with byte error control codes-a feasibility study

This paper addresses the relations between logic circuit synthesis, error model and error control codes so that the efficient reliable logic circuits can be obtained. We propose that single fault masking capability of a random logic circuit can be obtained by encoding its outputs in a byte error correcting code; this is equivalent to that of the triple module redundancy (TMR) technique. Similarly, byte error detecting code can be used to provide an equivalence of duplication. In this paper, we address the problems and issues related to the realization of byte-organized configuration where the byte error control codes can be applied. Some MCNC benchmark circuits are used as examples to demonstrate the feasibility of the proposed concept.

A class of error locating codes for byte-organized memory systems

Error locating codes (EL codes), first proposed by J.K. Wolf and B. Elspas (1963), have the potential to be used to identify the faulty module for fault isolation and reconfiguration in fault-tolerant computer systems. A new class of EL codes suitable for memory systems organized with b-bit (b/spl ges/2) byte-organized semiconductor memory chips which are mounted on memory cards each having B-bit width is proposed. The proposed linear code, called S/sub b/B/EL code, identifies erroneous memory card locations containing a faulty byte-organized chip. Another important linear code proposed in this work, SEC-S/sub b/B/EL code, corrects single bit errors induced by alpha particles and, for byte errors, it locates erroneous card positions containing a faulty chip. The design methods of the proposed codes are described, and the decoding hardware and the error detection capabilities are evaluated.

Burst Error Recovery for Huffman Coding

Although data compression is popularly used, compressed data have a problem that they are very sensitive to errors. This paper proposes a single burst error recovery method for Huffman coding by using the bidirectionally decodable Huffman coding. Computer simulation shows that the proposed method can recover 2.5lburst bits burst error with high probability, where lburst is the maximum length of burst errors which the proposed method is expected to be able to recover.

Metrics of error locating codes

Error locating codes were first presented by Wolf and Elspas (1963). Error locating codes suitable for byte-organized semiconductor memory systems have been proposed. It is apparent that the code conditions of error correcting/detecting codes are expressed by the Hamming distance, but, on the other hand, those of error locating codes cannot always be expressed by only the Hamming distance. That is, the algebraic structure of the error locating codes has not yet been clarified. This paper defines a new metric for the error locating codes and then deduces the necessary and sufficient conditions of the codes by using the metric. These conditions clarify the relation between the code functions of error location and error correction/detection.

Code design and decoding methods for burst error locating codes

Error locating code, a class of error control codes, can indicate the location of the error and is useful to fault diagnosis in computer systems and reduction of the retransmission cost in communication systems. The authors proposed two types of burst error locating codes called B/sub 1/EL codes and SEC-B/sub 1/EL codes. Since single-hit errors are more probable than burst errors, the latter codes having single-bit error correction capability are practical. However, the code length of the existing SEC-B/sub 1/EL code is not long. This paper proposes efficient SEC-B/sub 1/EL codes having longer code length. The proposed code is obtained from a parity check matrix of burst error connecting codes. The number of the frames in the proposed SEC-B/sub 1/EL codes increases as the codelength increases, while that in the existing SEC-B/sub 1/EL codes infixed. This also proposes both parallel and serial decoding methods of the proposed code in order to apply this code to both computer and communication systems. The parallel decoder is implemented by hardware description language and its circuit area is evaluated. Code evaluation says that the code length of the proposed code is about 1.1 times as long as that of the existing code and that decoder circuit area of the proposed code is 20 to 40 percent of that of burst error correcting Fire code.

Single-bit error correcting and burst error locating codes

The error location function of codes was first proposed by Wolf and Elspas in 1963 lying midway between error correction and error detection. In 1982, Dass proposed burst error locating codes. These codes, however, have a problem that they cannot locate burst errors which occur at the boundary of the two adjacent subblocks. From this point, the authors proposed a new class of burst error locating codes indicating an erroneous frame, called single bit error correcting and l-bit burst error locating codes, or SEC-B/sub l/EL codes. Here, the frame is a set of continuous symbols in a codeword and adjacent frames are partially overlapped in order to make any burst errors not exceeding the maximum size of the frame be included in at least one frame. The proposed codes, however, have more check-bits than burst error correcting fire codes for longer information-bit length. This paper proposes a new code design method of the SEC-B/sub l/EL codes having less check-bits than the burst error correcting fire codes.

Error recovery for Ziv-Lempel coding by using UEP schemes

Lossless data compression, such as arithmetic coding and Ziv-Lempel coding, is widely used for text compression. Since errors in compressed data have a great influence on the decompression, error control for the compressed data is necessary. From this view point, the authors propose a burst error recovery method in arithmetic coding. They consider error recovery schemes for LZW coding and LZ77 coding by using unequal error protection (UEP) schemes, which protect the important parts of the compressed data more strongly.