Masato Noborio

Interface Properties of Metal-Oxide-Semiconductor Structures on 4H-SiC{0001} and (1120) Formed by N2O Oxidation

4H-SiC(0001), (0001), and (1120) have been directly oxidized by N2O at 1300°C, and metal–oxide–semiconductor (MOS) interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC(0001), (0001) and (1120) faces have shown effective channel mobilities of 26, 43, and 78 cm2/Vs, respectively. Secondary ion mass spectrometry analyses have revealed a clear pileup of nitrogen atoms near the MOS interface. The thickness of the interfacial transition layer can be decreased by N2O oxidation. The crystal face dependence of the interface structure is discussed. A simple consideration of chemistry indicates that NO, generated from the decomposition of N2O, may be a more efficient oxidant of carbon than O2.

4H–SiC Lateral Double RESURF MOSFETs With Low on Resistance

Designing and fabrication of 4H-SiC (0001) lateral MOSFETs with a double reduced surface field (RESURF) structure have been investigated to reduce ON resistance. In order to achieve high breakdown voltage, a two-zone RESURF structure was also employed in addition to the double RESURF structure. The simulated double RESURF MOSFETs with optimum doses exhibit slightly higher breakdown voltage and lower drift resistance than the simulated single RESURF MOSFETs. The double RESURF structure is attractive to suppress oxide breakdown at gate edge. After the device simulation for dose optimization, the 4H-SiC two-zone double RESURF MOSFETs have been fabricated by using a self-aligned process. The fabricated MOSFET has demonstrated a high breakdown voltage of 1380 V and a low ON resistance of 66 mOmegamiddotcm2 (including a drift resistance of 24 mOmegamiddotcm2). The drift resistance of the fabricated double RESURF MOSFETs is only 50% or even lower than that of the single RESURF MOSFETs

Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N2O Annealing

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.

P-Channel MOSFETs on 4H-SiC {0001} and Nonbasal Faces Fabricated by Oxide Deposition and

In this paper, we have investigated 4H-SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited SiO2 followed by N2O annealing. In addition to deposited oxides, dry-O2-grown oxides and N2O-grown oxides were also adopted as the gate oxides of SiC p-channel MOSFETs. The MOSFETs have been fabricated on the 4H-SiC (0001), (0001macr), (033macr8), and (112macr0) faces. The (0001) MOSFETs with deposited oxides exhibited a relatively high channel mobility of 10 cm2/V ldr s, although a mobility of 7 cm2/V ldr s was obtained in the (0001) MOSFETs with N2O-grown oxides. The channel mobility was also increased by utilizing the deposited SiO2 in the MOSFETs fabricated on nonbasal faces, although the MOSFETs on (0001macr) were not operational. Compared with the thermally grown oxides, the deposited oxides annealed in N2O are effective in improving the performance of 4H-SiC p-channel MOSFETs.

\hbox{N}_{2}\hbox{O}

SiN_x / SiO₂ stack-gate structures, followed by N₂O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N₂O at 1300degC. When the MIS capacitor with a SiN_x / SiO₂ thickness of 10 nm/50 nm was annealed in N₂O for 2 h, the interface trap density at E_c - 0.2 eV is below 1 X 10¹¹ cm ^-2eV^-1. Oxidation of SiN_x during N₂O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiN_x / SiO₂ stack-gate structure annealed in N₂O demonstrate a reasonably high channel mobility of 32 cm² / V ldr s on the (0001)Si face and 40 cm²/ V ldrs on the (0001) C face.

Annealing

In this work, the electrical characteristics and the reliability of 80nm thick deposited oxides annealed in NO and N2O on the 4H-SiC Si-face for gate oxide application in MOS devices is analyzed by C-V, I-V measurements and by constant current stress. Compared to thermally grown oxides, the deposited oxides annealed in N2O or NO showed improved electrical properties. Dit-values lower than 1011cm-2eV-1 have been achieved for the NO sample. The intrinsic QBD-values of deposited and annealed oxides are one order of magnitudes higher than the highest values reported for thermally grown oxides. Also MOSFETS were fabricated with a channel mobility of 20.05 cm2/Vs for the NO annealed deposited oxide. Furthermore annealing in NO is preferred to annealing in N2O regarding µFE- and QBD-values.

4H-SiC MIS Capacitors and MISFETs With Deposited

The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

\hbox{SiN}_{x}/ \hbox{SiO}_{2}

Inversion- and depletion-type GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated on p- and n--type GaN epitaxial layers, respectively, grown on n+-type on-axis 4H-SiC(0001) substrates. After gate SiO2 was deposited by plasma-enhanced chemical vapor deposition at 350 °C, high-temperature annealing in N2 was carried out to modify the interface. The channel mobility was enhanced with increasing annealing temperature. The device annealed in N2 at 1100 °C after SiO2 deposition showed an inversion channel mobility of 108 cm2V-1s-1 at a gate voltage of 15 V. The authors also fabricated MOS capacitors on n--type GaN and characterized the interface state density at the SiO2/GaN interface from capacitance–voltage measurements using the Terman method, of which density was estimated to be in the range of (6–10)×1011 cm-2eV-1 at an energy level of 0.2 eV below the conduction band edge. The interface state density tended to decrease with increasing annealing temperature, resulting in the improvement of the channel mobility.

Stack-Gate Structures

Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.