Tsunenobu Kimoto

Power Conversion With SiC Devices at Extremely High Ambient Temperatures

This paper evaluates the capability of SiC devices for operation under extremely high ambient temperatures. To this end, the authors packaged SiC JFET and Schottky barrier diodes (SBD) in thermally stable packages and built a high-temperature inductor to be evaluated in a DC-DC buck converter. The DC characteristics of the SiC JFET devices were first measured at ambient temperatures ranging from room temperature up to 450 degC. The experimental results show that the device can operate at 450 degC, which is impossible for conventional Si devices, but as expected the current capability of the SiC JFET diminishes with rising temperatures. A DC-DC converter was then designed and built in accordance with the static characteristics of the SiC JFETs that were measured under extremely high ambient temperatures. The converter was tested up to an ambient temperature of 400 degC. The conduction loss of the SiC JFET increases slightly, as predicted from its DC characteristics, but its switching characteristics hardly change with increasing temperatures. Thus, SiC devices are well suited for operation in harsh temperature environments

Investigation of carrier lifetime in 4H-SiC epilayers and lifetime control by electron irradiation

Carrier lifetimes in 4H-SiC epilayers are investigated by differential microwave photoconductivity decay measurements. When the Z1∕2 concentration is higher than 1013cm−3, the Z1∕2 center works as a recombination center. In this case, carrier lifetimes show positive dependence on the injection level (number of irradiated photons). On the other hand, other recombination processes such as surface recombination limit the lifetime when the Z1∕2 concentration is lower than 1013cm−3. In this case, carrier lifetimes have decreased by increasing the injection level. By controlling the Z1∕2 concentration by low-energy electron irradiation, the lifetime control has been achieved.

Reduction of Deep Levels and Improvement of Carrier Lifetime in n-Type 4H-SiC by Thermal Oxidation

Significant reduction of major deep levels in n-type 4H-SiC(0001) epilayers by means of thermal oxidation is demonstrated. By thermal oxidation of epilayers at 1150–1300 °C, the concentration of the Z1/2 and EH6/7 centers has been reduced from (0.3–2)×1013 cm-3 to below the detection limit (1×1011 cm-3). The depth-profile analysis of the Z1/2 center has revealed that the Z1/2 center is eliminated to a depth of about 50 µm from the surface after thermal oxidation at 1300 °C for 5 h. The carrier lifetime in an n-type 4H-SiC epilayer measured by differential microwave photoconductance decay has been significantly improved from 0.73 µs (as-grown) to 1.62 µs (after oxidation: 1300 °C, 5 h×2). The reduction mechanism of the Z1/2 and EH6/7 centers is discussed.

21-kV SiC BJTs With Space-Modulated Junction Termination Extension

We report here 20-kV-class small-area (0.035 mm2) 4H-SiC bipolar junction transistors. We implemented edge termination techniques featuring two-zone junction termination extension and space-modulated rings. On-state characteristics showed a current gain of 63 and a specific on-resistance of 321 mΩ·cm2, which is slightly below the SiC unipolar limit. We achieved the open-base blocking voltage of 21 kV at a leakage current of 0.1 mA/cm2, which is the highest blocking voltage among any semiconductor switching devices.

Impacts of recombination at the surface and in the substrate on carrier lifetimes of n-type 4H–SiC epilayers

After remarkable reduction in the Z1/2 center in n-type 4H–SiC epilayers, the measured carrier lifetimes can be severely affected by other recombination paths. Impacts of carrier recombination at the surface as well as in the substrate are investigated in detail by using numerical simulation based on a diffusion equation. The simulation reveals that a very thick (>100 μm) epilayer is required for accurate measurement of carrier lifetimes if the bulk lifetime in the epilayer is longer than several microsecond, due to the extremely short lifetimes in the substrate. The fast decay often observed at the initial stage of decay curves can be explained by fast recombination at the surface and in the substrate. In experiments, the carrier lifetime is improved from 0.69 to 9.5 μs by reducing the Z1/2 center via two-step thermal treatment (thermal oxidation and Ar annealing) for a 148-μm-thick n-type epilayer. This lifetime must be still, to large extent, affected by the recombination at the surface and in the subs...

Stability of deep centers in 4H-SiC epitaxial layers during thermal annealing

N-type epitaxial 4H-SiC layers grown by hot-wall chemical vapor deposition were investigated with regard to deep centers by capacitance-voltage measurements and deep level transient spectroscopy (DLTS). The DLTS spectra revealed that the concentrations of deep centers were reduced by one order of magnitude by annealing at 1700°C, compared to those in an as-grown material. The Z1∕2 center with an energy level of 0.59±0.03eV and the EH6∕7 center with an energy level of 1.66±0.11eV below the conduction band edge are annealed out at a temperature of 1700°C or higher.

Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zone junction termination extension (JTE) have been employed to achieve a high breakdown voltage (ges 10 kV). The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of 1.1 times 1013 cm-2 has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.

Space-Modulated Junction Termination Extension for Ultrahigh-Voltage p-i-n Diodes in 4H-SiC

An edge termination method, referred to as space-modulated junction termination extension (SMJTE) combined with a mesa structure, is presented for ultrahigh-voltage p-i-n diodes in 4H-SiC. Numerical device simulations have been performed for over 15-kV-class 4H-SiC p-i-n diodes with the proposed edge termination. The structure exhibits a high breakdown capability with an improved tolerance for the deviation of impurity dose in the JTE region. Unlike conventional multi-implantation, the proposed termination technique utilizes a single-step implantation with a single mask. A desired laterally tapered doping profile is achieved by fragmenting a conventional JTE region using relatively wide spaces. The simple process of the proposed edge termination makes it applicable to fabrication of various high-voltage devices in 4H-SiC.

Detection and depth analyses of deep levels generated by ion implantation in n- and p-type 4H-SiC

The authors investigated deep levels in the whole energy range of bandgap of 4H-SiC, which are generated by low-dose N+, P+, and Al+ implantation, by deep level transient spectroscopy (DLTS). Ne+-implanted samples have been also prepared to investigate the pure implantation damage. In the n-type as-grown material, the Z1∕2 (EC−0.63eV) and EH6∕7 (EC−1.6eV) centers are dominant deep levels. At least, seven peaks (IN1, IN3–IN6, IN8, and IN9) have emerged by implantation and annealing at 1000°C in the DLTS spectra from all n-type samples, irrespective of the implanted species. After high-temperature annealing at 1700°C, however, most DLTS peaks disappeared, and two peaks, IN3 and IN9, which may be assigned to Z1∕2 and EH6∕7, respectively, survive with a high concentration over the implanted atom concentration. In the p-type as-grown material, the D (EV+0.40eV) and HK4 (EV+1.4eV) centers are dominant. Two peaks (IP1 and IP3) have emerged by implantation and annealing at 1000°C, and four traps IP2 (EV+0.39eV), ...

Analytical model for reduction of deep levels in SiC by thermal oxidation

Two trap-reduction processes, thermal oxidation and C+ implantation followed by Ar annealing, have been discovered, being effective ways for reducing the Z1/2 center (EC – 0.67 eV), which is a lifetime killer in n-type 4H-SiC. In this study, it is shown that new deep levels are generated by the trap-reduction processes in parallel with the reduction of the Z1/2 center. A comparison of defect behaviors (reduction, generation, and change of the depth profile) for the two trap-reduction processes shows that the reduction of deep levels by thermal oxidation can be explained by an interstitial diffusion model. Prediction of the defect distributions after oxidation was achieved by a numerical calculation based on a diffusion equation, in which interstitials generated at the SiO2/SiC interface diffuse to the SiC bulk and occupy vacancies related to the origin of the Z1/2 center. The prediction based on the proposed analytical model is mostly valid for SiC after oxidation at any temperature, for any oxidation tim...