Masato Takita

A 256 Mb SDRAM using a register-controlled digital DLL

This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

A dramatic reduction of the internal operating voltage and a high-speed clocking technique are the keys to low-power, high-speed memory technologies. When the memory core supply voltage is reduced to below 1.8 V, the electrical performance significantly degrades in two ways. First, sensing speed slows due to the noticeable threshold voltage of source-floated transistors. Second, the necessity of a relatively high Vpp voltage for the word lines may require a tripler-pumping circuit that significantly increases power. In this 1 Gb synchronous DRAM, the bitline precharge level is Vss (ground). The word line reset level is -0.5 V to prevent cell leakage current while reducing the threshold voltage of pass transistors and thus to eliminate word line boosting. Power consumption is thus decreased since inefficient tripler boosting is no longer necessary. This technology is also suitable for merged DRAM and logic circuits.