Satoshi Eto

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line

A dramatic reduction of the internal operating voltage and a high-speed clocking technique are the keys to low-power, high-speed memory technologies. When the memory core supply voltage is reduced to below 1.8 V, the electrical performance significantly degrades in two ways. First, sensing speed slows due to the noticeable threshold voltage of source-floated transistors. Second, the necessity of a relatively high Vpp voltage for the word lines may require a tripler-pumping circuit that significantly increases power. In this 1 Gb synchronous DRAM, the bitline precharge level is Vss (ground). The word line reset level is -0.5 V to prevent cell leakage current while reducing the threshold voltage of pass transistors and thus to eliminate word line boosting. Power consumption is thus decreased since inefficient tripler boosting is no longer necessary. This technology is also suitable for merged DRAM and logic circuits.

A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of 0.5 mm/sup 2/.