Masatoshi Yoshimura

A III–V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction

In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.

Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping technique.

We report changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistors by the Zn-pulsed doping technique for InAs nanowire channels. The doping of the nanowire channel moderately changes turn-on voltage from negative to positive voltage, while keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. The formation of pseudointrinsic InAs segment is found to be important to make a normally off transistor with a steep subthreshold slope.

GaAs/InGaP Core-Multishell Nanowire-Array-Based Solar Cells

Semiconductor nanowires (NWs) are good candidate for light-absorbing material in next generation photovoltaic and III–V NW-based multi-heterojunction solar cells using lattice-mismatched material system are expected as high energy-conversion efficiencies under concentrated light. Here we demonstrate core–shell GaAs NW arrays by using catalyst-free selective-area metal organic vapor phase epitaxy (SA-MOVPE) as a basis for multijunction solar cells. The reflectance of the NW array without any anti-reflection coating showed much lower reflection than that of a planar wafer. Next we then fabricated core–shell GaAs NW array solar cells with radial p–n junction. Despite the low reflectance, the energy-conversion efficiency was 0.71% since a high surface recombination rate of photo-generated carriers and poor ohmic contact between the GaAs and transparent indium–tin-oxide (ITO) electrode. To avoid these degradations, we introduced an InGaP layer and a Ti/ITO electrode. As a result, we obtained a short-circuit current of 12.7 mA cm-2, an open-circuit voltage of 0.5 V, and a fill factor of 0.65 for an overall efficiency of 4.01%.

Indium Phosphide Core–Shell Nanowire Array Solar Cells with Lattice-Mismatched Window Layer

We report surface-passivated core–shell InP nanowire array solar cells fabricated using catalyst-free selective-area metal organic vapor phase epitaxy. Reflectance measurements confirm enhanced light absorption due to significantly reduced reflectance over a wide spectral range. The wide-band-gap outer shell layer of core-multishell nanowires effectively passivates the large surface area of the nanowires, increasing the short-circuit current density and elevating the energy conversion efficiency by 6.35% under AM1.5G illumination. This passivation technique could open a new approach to nanowire-based photovoltaics with higher energy efficiency.

Integration of III-V nanowires on Si: From high-performance vertical FET to steep-slope switch

In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.

Position-Controlled III–V Compound Semiconductor Nanowire Solar Cells by Selective-Area Metal–Organic Vapor Phase Epitaxy

We demonstrate position-controlled III–V semiconductor nanowires (NWs) by using selective-area metal–organic vapor phase epitaxy and their application to solar cells. Efficiency of 4.23% is achieved for InP core–shell NW solar cells. We form a ‘flexible NW array’ without a substrate, which has the advantage of saving natural resources over conventional thin film photovoltaic devices. Four junction NW solar cells with over 50% efficiency are proposed and discussed.

Indium tin oxide and indium phosphide heterojunction nanowire array solar cells

Heterojunction solar cells were formed with a position-controlled InP nanowire array sputtered with indium tin oxide (ITO). The ITO not only acted as a transparent electrode but also as forming a photovoltaic junction. The devices exhibited an open-circuit voltage of 0.436 V, short-circuit current of 24.8 mA/cm2, and fill factor of 0.682, giving a power conversion efficiency of 7.37% under AM1.5 G illumination. The internal quantum efficiency of the device was higher than that of the world-record InP cell in the short wavelength range.

Growth and Characterization of InGaAs Nanowires Formed on GaAs(111)B by Selective-Area Metal Organic Vapor Phase Epitaxy

We fabricated InGaAs nanowires (NWs) in SiO2 mask openings on a GaAs(111)B substrate at growth temperatures of 600–700 °C using catalyst-free selective-area metal organic vapor phase epitaxy. At a growth temperature of 600 °C, particle-like depositions occurred, but they decreased in number and density when the growth temperature was increased to 650 °C and disappeared above 675 °C. The heights and growth rates of the NWs increased when the growth temperature was increased and the mask opening diameter was decreased from 300 to 50 nm. Photoluminescence (PL) spectra measured for the NWs indicated a blue shift in the peak from 0.95 to 1.3 eV as the growth temperature was increased from 600 to 700 °C, indicating an increase in the Ga composition from 62 to 88% in the InGaAs NWs.

Vertical In 0.7 Ga 0.3 As nanowire surrounding-gate transistors with high-k gate dielectric on Si substrate

In this paper, direct integration of vertical InGaAs nanowires (NWs) on Si substrate without buffering techniques, and fabrication of InGaAs NW surrounding-gate transistors (SGTs) with high-k gate dielectrics is reported for the first time. Furthermore, we investigated a passivation technique using InGaAs/InP/InAlAs/InGaAs core-multishell (CMS) structure, and showed enhancement of transconductance (G<inf>m</inf>) and I<inf>ON</inf>/I<inf>OFF</inf> ratio of the InGaAs CMS NW-SGT. The peak G<inf>m</inf> for the InGaAs-related CMS NW-SGT was 500 µS/µm at V<inf>DS</inf> of 1.00V, and I<inf>ON</inf>/I<inf>OFF</inf> ratio was ∼ 10⁹.