Katsuhiro Tomioka

A III–V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

GaAs/AlGaAs Core Multishell Nanowire-Based Light-Emitting Diodes on Si

We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm(2)), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III-V NWs on Si.

III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications

III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled growth of InAs, GaAs, and InGaAs NWs on Si by selective-area growth, and discuss how to control growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial growth with misfit dislocations and coherent growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Tunnel field-effect transistor using InAs nanowire/Si heterojunction

We report on fabrication of tunnel field-effect transistor with III-V nanowire (NW)/Si heterojunction and surrounding-gate structure. The device fabricated by selective-area growth of an n+-InAs/undoped-InAs axial NW on a p+-Si(111) substrate showed switching behavior with an average subthreshold slope (SS) of 104 mV/dec under reverse bias condition. The switching behavior appeared under small supply voltage (Vds=50 mV). Transmission electron microscopy revealed misfit dislocation formed at the interface degraded the SS and ON-state current. Coherent growth without misfit dislocations would promise realization of steep-slope transistor with a SS of <60 mV/dec.

Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction

In this paper, we propose tunneling field-effect transistors (TFETs) using III-V nanowire (NW)/Si heterojunctions and experimentally demonstrate steep-slope switching behaviors using InAs NW/Si heterojunction TFET with surrounding-gate architecture and high-k dielectrics. Control of resistances in this device structure is important for achieving steep-slope switching. A minimum subthreshold slope (SS) of the TFET is 21 mV/dec at VDS of 0.10 - 1.00 V.

Vertical Surrounding Gate Transistors Using Single InAs Nanowires Grown on Si Substrates

We report on the fabrication and characterization of vertical InAs nanowire channel field effect transistors (FETs) with high-k/metal gate-all-around structures. Single InAs nanowires were grown on Si substrates by the selective-area metalorganic vapor phase epitaxy method. The resultant devices exhibited n-channel FET characteristics with a threshold voltage of around -0.1 V. The best device exhibited maximum drain current (I DSmax/w G), maximum transconductance (g mmax/w G), on–off ratio (I ON/OFF), subthreshold slope (SS) of 83 µA/µm, 83 µS/µm, 104, and 320 mV/decade, respectively, for a nanowire diameter of 100 nm.

Structural transition in indium phosphide nanowires.

We study the catalyst-free growth of InP nanowires using selective-area metalorganic vapor phase epitaxy (SA-MOVPE) and show that they undergo transition of crystal structures depending on the growth conditions. InP nanowires were grown on InP substrates where the mask for the template of the growth was defined. The nanowires were grown only in the opening region of the mask. It was found that uniform array of InP nanowires with hexagonal cross section and with negligible tapering were grown under two distinctive growth conditions. The nanowires grown in two different growth conditions were found to exhibit different crystal structures. It was also found that the orientation and size of hexagon were different, suggesting that the difference of the growth behavior. A model for the transition of crystal structure is presented based on the atomic arrangements and termination of InP surfaces. Photoluminescence measurement revealed that the transition took place for nanowires with diameters up to 1 microm.

Zinc blende and wurtzite crystal phase mixing and transition in indium phosphide nanowires.

Indium phosphide (InP) nanowires, which have crystal phase mixing and transition from zinc blende (ZB) to wurtzite (WZ), are grown in intermediate growth conditions between ZB and WZ by using selective-area metalorganic vapor phase epitaxy (SA-MOVPE). The shape of InP nanowires is tapered unlike ZB or WZ nanowires. A growth model has been developed for the tapered nanowires, which is simply described as the relationship between tapered angle and the ratio of ZB and WZ segments. In addition, the peak energy shift in photoluminescence measurement was attributed to the quantum confinement effect of the quantum well of the ZB region located in the polytypic structure of ZB and WZ in nanowires.

Electrical Characterizations of InGaAs Nanowire-Top-Gate Field-Effect Transistors by Selective-Area Metal Organic Vapor Phase Epitaxy

Single InGaAs nanowire-top-gate metal–semiconductor field-effect transistors (MESFETs) were fabricated and characterized. Silicon-doped n-InGaAs nanowires (with a typical diameter of 100 nm) were grown by catalyst-free selective-area metal–organic vapor-phase epitaxy (SA-MOVPE). The FETs of single nanowires on SiO2-coated Si substrates were fabricated by defining metal contacts at both ends of the nanowires and the metal top gate between contacts. According to the measurements of drain current–voltage and gate transfer characteristics, the top-gate MESFETs exhibited significant enhancements in device performance characteristics compared with FETs under back-gate operation; that is, a peak transconductance of 33 mS/mm and a current on–off ratio of 103 were obtained. A possibility for further improvements in FET characteristics was also considered.

Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping technique.

We report changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistors by the Zn-pulsed doping technique for InAs nanowire channels. The doping of the nanowire channel moderately changes turn-on voltage from negative to positive voltage, while keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. The formation of pseudointrinsic InAs segment is found to be important to make a normally off transistor with a steep subthreshold slope.