Masaya Iwamoto

Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data

A non-quasi static large-signal FET model is presented incorporating self-heating and other multiple timescale dynamics necessary to describe the large-signal behavior of III–V FET technologies including GaAs and GaN. The model is unique in that it incorporates electro-thermal and trapping dynamics (gate lag and drain lag) into both the model current source and the model nonlinear output charge source, for the first time. The model is developed from large-signal waveform data obtained from a modern nonlinear vector network analyzer (NVNA), working in concert with an output tuner and bias supplies. The dependences of Id and Qd on temperature, two trap states, and instantaneous terminal voltages are identified directly from NVNA data. Artificial neural networks are used to represent these constitutive relations for a compiled implementation into a commercial nonlinear circuit simulator (Agilent ADS). Detailed comparisons to large-signal measured data are presented.

Device modeling with NVNAs and X-parameters

This paper reviews and contrasts two complementary device modeling approaches based on data readily obtainable from a nonlinear vector network analyzer (NVNA) [1]. The first approach extends the application of waveform data to improve the characterization, parameter extraction, and validation methodologies for “compact” transistor models. NVNA data is used to train artificial neural network -based constitutive relations depending on multiple coupled dynamic variables, including temperature and trap states for an advanced compact model suitable for GaAs and GaN transistors. The second approach is based on load-dependent X-parameters* [2], [3], [5], [6], measured using an output tuner working with the NVNA. It is demonstrated that X-parameters measured versus load at the fundamental frequency predict well the independent effects of harmonic load tuning on a 10W GaN packaged transistor without having to independently control harmonic loads during characterization. A comparison of the respective merits of the two approaches is presented.

Measurement-Based Non-Quasi-Static Large-Signal FET Model Using Artificial Neural Networks

A new measurement-based FET model is presented which combines non-quasi-static dynamics formulated with constitutive relations derived using adjoint and conventional artificial neural networks (ANN). The new model features smoother constitutive relations than spline-based methods while maintaining the non-quasi-static dynamics for accurate distortion simulations. Additionally, this work demonstrates, for the first time, the construction of an adjoint-trained ANN-based high-frequency drain current constitutive relation (accounting for dispersion due to traps and thermal effects in III-V FETs), along with drain and gate terminal charges from measured bias-dependent data. The model is implemented in Agilent ADS and validated with nonlinear measurements on a 0.25mum GaAs pHEMT device

Scaling of X-parameters for device modeling

The relationships between X-parameters of a given transistor and a second transistor geometrically scaled with respect to the first are derived and presented for the first time. The different types of X-parameters scale differently. These relationships enable X-parameters measured on a fixed size of transistor, diode, or other similar test structure to be scaled to other sizes and produce X-parameter functions as continuous function of size (e.g. total gate width or area). This capability endows X-parameters with a key property of conventional scalable “compact models”, enabling an improved MMIC design capability where size/geometry is a key design degree of freedom. The scalable X-parameters for device modeling are implemented in a commercial nonlinear simulator. The theoretical predictions are validated with numerical results from simulation-based extractions and experimental nonlinear measurements taken with an NVNA on active devices of different sizes.

Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends

This paper reviews three modern transistor modeling flows enabled by large-signal waveform and/or X-parameter1 measurements from a commercially available nonlinear vector network analyzer (NVNA) instrument. NVNA transistor characterization more safely exercises the device over a wider operating domain than is possible with conventional DC and linear S-parameter measurements, is more indicative of the device large-signal response in actual use conditions, provides data at much faster timescales than pulsed I-V methods, and provides large-signal model validation as a free additional benefit. In the first flow considered, NVNA waveform data is used as a target to extract and tune compact model parameter values and for model validation under large-signal conditions. In the second flow, NVNA waveform data is used to directly construct the multi-variate nonlinear current-source and charge-based nonlinear capacitor functions of an advanced electrothermal and trap-dependent compact model suitable for GaAs and GaN FETs, effectively bypassing the need for explicit model constitutive relation formulation. The final approach is based on the X-parameter measurement and behavioral modeling framework supported by the NVNA, producing nonlinear transistor models directly in the frequency domain. Recent advances in X-parameter methods for transistors, including simple scalability with geometry, show early potential for useful device models, under certain conditions, without the requirement of specifying an internal topology or equivalent circuit at all.

Drain-Source Symmetric Artificial Neural Network-Based FET Model with Robust Extrapolation Beyond Training Data

A large-signal FET model based on artificial neural networks (ANNs) is extended for rigorous intrinsic drain-source symmetry and robust extrapolation beyond the range of training data. Enhanced ANN architectures and training algorithms constrain the five nonlinear model state functions to transform according to the discrete symmetry rules related to the device invariance with respect to intrinsic drain-source exchange. This extends the applicability of the previous ANN-based model to situations where the instantaneous voltage crosses Vds= 0, such as switches and mixers. The model is compiled in Agilent ADS, together with advanced extrapolation routines extending the model beyond the range of training data for improved convergence. The model has been generated for FETs from several III-V semiconductor processes, and validated with extensive independent small and large-signal measurements.

High efficiency current-mode class-D amplifier with integrated resonator

This paper shows that current mode class-D (CMCD) amplifiers with integrated parallel LC resonator can achieve high efficiency at RF frequencies. In contrast to the conventional class-D amplifier, output shunt capacitance discharge loss is eliminated in a CMCD amplifier topology by satisfying the zero voltage switching (ZVS) condition. To reduce parasitic resistance, bondwires are utilized to implement a high Q inductor in the LC resonator. An experimental CMCD amplifier with collector efficiency of 78.5% at output power of 29.5dBm (0.89W) is demonstrated using GaAs HBTs at 700 MHz.

III–V FET high frequency model with drift and depletion charges

A formulation and implementation of the III–V FET nonlinear charge model decomposed into a combination of univariate voltage depletion charges and a bivariate mixed voltage-current dependent “drift” charge is presented. The concept is based on the principles used in well-established BJT models where depletion and diffusion charges are modeled separately. Analogous to the diffusion charge in BJT models, the drift charge represents the mobile carriers in the channel of the FET. The total charge depends on the depletion capacitances, drain current, and transit time, which links the FET charge model directly to the physical operation of the device. A measurement-based prototype model is demonstrated for a GaAs pHEMT using artificial neural networks to define the analytical constitutive relations of the depletion and drift charges.