Masoud Babaie

An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability

In this paper, we propose a new class of operation of an RF oscillator that minimizes its phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second-harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F 2 operation. As a result, the noise contribution of the tail current transistor on the total phase noise can be significantly decreased without sacrificing the oscillators voltage and current efficiencies. Furthermore, its special impulse sensitivity function (ISF) reduces the phase sensitivity to thermal circuit noise. The prototype of the class-F 2 oscillator is implemented in standard TSMC 65 nm CMOS occupying 0.2 mm 2 . It draws 32-38 mA from 1.3 V supply. Its tuning range is 19% covering 7.2-8.8 GHz. It exhibits phase noise of -139 dBc/Hz at 3 MHz offset from 8.7 GHz carrier, translated to an average figure-of-merit of 191 dBc/Hz with less than 2 dB variation across the tuning range. The long term reliability is also investigated with estimated >10 year lifetime.

25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <;1MHz, which practically implies all cellular phones. A previously published noise-filtering technique [1] and adding resistors in series with gm-device drains [2] have shown significant reduction of the 1/f3 oscillator PN corner. However, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillators 1/f3 phase noise. We demonstrate that if the ω0 tank exhibits an auxiliary resonance at 2ω0, thereby forcing this current harmonic to flow into the equivalent resistance of the 2ω0 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor-and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential-and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.

A study of RF oscillator reliability in nanoscale CMOS

In this paper, we investigate the nature of oxide breakdown and stress-related degradation mechanisms in MOS transistors. The MOS breakdown time is quantified based on exponential-law and defect-generation models versus the oxide-thickness, gate area, temperature and voltage stress at a given cumulative failure. As a consequence, a design guide is presented to estimate the time dependent dielectric breakdown of any analog circuit. Based on reliability analysis, the lifetime of the recently introduced class-F oscillator is evaluated for both thin and thick oxide options in TSMC 65-nm CMOS process.

Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM

The design of CMOS oscillators for the strict phase noise (PN) requirements of cellular standards, as well as low power consumption and thus high figure-of-merit (FoM), is very challenging. For example, in a GSM mobile station (MS), the PN requirement is -162dBc/Hz at 20MHz offset from a 915MHz carrier for a local oscillator (LO). On the other hand, LO power efficiency is a critical factor for a long-lasting battery life.

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier

This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of -100 dBc/Hz at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS

We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits -157 dBc/Hz at 20MHz offset at ~2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized 6 ps resolution for -108 dBc/Hz in-band phase noise. FREF spur is ultra-low at <;-94 dBc. The ADPLL supports a 2-point modulation and consumes 12mW while occupying 0.22mm2, thus demonstrating both 72% power and 38% area reductions over prior records.

A wideband 60 GHz class-E/F 2 power amplifier in 40nm CMOS

This paper presents a fully integrated 60 GHz power amplifier in 40nm CMOS that reaches the highest reported product of power-added efficiency and bandwidth. It is achieved through low/moderate coupling-factor transformers in the preliminary stages and a proper second harmonic termination of the output stage, such that it can operate as a class-E/F2 switched-mode PA at the saturation point. The three-stage PA delivers 17.9dBm saturated output power with 20% peak PAE. It demonstrates a bandwidth of 9.7 GHz with a peak gain of 21.6 dB.