Masoud Rezaei

A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter

In this paper, we present a novel level shifter circuit converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low-power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor contributing to increase the range of conversion voltages, while significantly reducing the conversion delay. Such a level-shifting capacitor is quickly charged, whenever the input signal detects a low-to-high transition, in order to boost internal voltage nodes, and quickly reach a high output voltage level. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18-

Low-power high-speed wireless transceivers and antennas for large-scale neural implants

\mu \text {m}

A power-efficient wide-range signal level-shifter

TSMC technology. The proposed circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100 Hz to 100 MHz. It has a propagation delay of 29 ns and a power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs.

A new charge balancing scheme for electrical microstimulators based on modulated anodic stimulation pulse width

Advancement in wireless and microsystems technology have ushered in new devices that can directly interface with the central nervous system for stimulating and/or monitoring neural circuitry. In this paper, we present the design of low-power CMOS integrated transceivers intended for utilization into large-scale multi-channel neural stimulating/monitoring implants. We discuss the design and the implementation of different modulation schemes and pulse shaping strategies within CMOS circuits, we review the most critical design challenges of this sensitive application, we compare different solutions and circuit topologies in terms of performance and safety, and we introduce a suitable implantable UWB antenna. In particular, we present an integrated transmitter (TX) and a receiver (RX) that are designed to share a single implantable antenna. The TX generates ultra wideband (UWB) impulses based on edge combining, and the RX uses a low-power ISM-2.4-GHz narrow-band OOK receiver topology. The RX can support downlink telemetry of neural stimulation applications with a data rate as high as 100 Mbps within a power budget of 5 mW, while the TX is designed to support uplink back telemetry with a data rate of up to 800 Mbps for power consumption of 5.36 mW for BPSK modulation. Finally, we present measurement results obtained with biological tissues that confirm the full functionality of the fabricated implantable transceiver.

A short-impulse UWB BPSK transmitter for large-scale neural recording implants

In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal. The proposed circuit has a small silicon area, low-power consumption and short propagation delay. Post-layout Simulation results for the proposed circuit implemented in a 0.18-μm 1P6M CMOS technology confirm that the power consumption of this circuit is extremely low comparing to other topologies, and is able to operate over a wide range of the input voltages from 50 mV to 1.8 V, and a wide range of frequencies from 100 Hz to 100 MHz. For both a 0.4 V and a 1.8V supply voltages, the proposed circuit has a propagation delay of 10.43 ns and a power consumption of 9.89 nW for a 10-kHz input signal.

A novel multichannel analog-to-time converter based on a multiplexed sigma delta converter

In this Paper, we propose a new method for safe electrical neural stimulation. Current mode digital-to-analog converters are used to generate the cathodic and the anodic stimulation phases. A sample-and-hold and a window comparator circuit are used to compare the voltage of the electrode and the tissue with a target value within a safe voltage range of −50 mV to +50 mV. When the electrode voltage falls below the lower bound or above the upper bound of such a safe voltage range, the anodic stimulation pulse width is modified in such a way that the electrode voltage remains in the safe range. High-level pulse shrinking (HLPS) and low-level pulse shrinking (HLPS) elements are used in digital part to modify anodic pulse width. Simulation results for the proposed circuit implemented in a 0.18μm 1P6M CMOS technology confirm proper functioning and show that the proposed circuit requires extremely low power compared to other charge balancing schemes, with a power consumption of 4.2 μW.

A wirelessly powered high-speed transceiver for high-density bidirectional neural interfaces

In this paper, a short-impulse ultra-wide band (UWB) transmitter is introduced to enable large-scale neural recordings within miniature brain implants including thousands of channels. The proposed impulse radio UWB transmitter uses a BPSK modulation scheme, the carrier signal of which uses only two delayed impulses to encode the transmitted signal. The proposed UWB transmitter has been implemented into a CMOS 180 nm technology. It occupies 300 μm × 230 μm, and consumes only 6.7 pJ/bit from a 1.8-V supply. Experimental results show that the transmitter has a bandwidth of 2.6 GHz to 5.6 GHz and achieves a maximum data rate of 800 Mbps, which outperforms existing low-power UWB transmitters for similar applications.

A fully implantable multichip neural interface with a new scalable current-reuse front-end

In this paper, a new sigma delta modulator based on a multiplexed input topology is proposed to decrease power consumption and size in implantable bio-interfacing systems. An opamp sharing technique is employed in order to process several input sequentially. The proposed sigma delta modulator integrates each input separately and stores the integrated value inside a dedicated capacitor. We show that the resulting transfer function of the modulator is equivalent for all channels. The proposed circuit has been implemented in a 180-nm TSMC process. The circuit includes 4 channels and consumes 11.5 μW per channel, provides an ENOB of 7.8 bits, and presents a bandwidth of 10 kHz. The chip area for the proposed design is 150 μm × 135 μm for 4 multiplexed inputs.

Ultra-low distortion linearized pseudo-RC low-pass filter

This paper presents a wirelessly powered, fully-integrated, low-power full-duplex transceiver to support high-density and bidirectional neural implants. The transmitter (TX) uses impulse radio ultra-wide band based on an edge combining approach, and the receiver (RX) uses a 2.4-GHz on-off keying narrow band topology. The proposed transceiver provides dual band 500-Mbps TX uplink data rate and 100 Mbps RX downlink data rate, and it is fully integrated into standard TSMC 0.18-μm CMOS within a total size of 0.8 mm2. The total measured power consumption is 10.4 mW in full duplex mode (5 mW at 100 Mbps for RX, and 5.4 mW at 800 Mbps or 6.7 pJ/bit for TX). The transceiver is wirelessly powered up by a smart home-cage system based on overlapped multicoil arrays through a thin implantable multicoil receiver of 1×1 cm2 of size, implanted bellow the scalp of a laboratory mouse, and integrated power management circuits. This inductive system is designed to deliver up to 35.5 mW of power delivered to the load from a 13.56-MHz carrier signal with an overall power transfer efficiency above 5% across a separation distance ranging from 3 cm to 5 cm.

A 110-nW in-channel sigma-delta converter for large-scale neural recording implants

This paper presents a fully implantable brain machine interface based on a new CMOS system-on-a-chip (SOC) including a low-power multi-channel current-reuse analog front-end (AFE), a multi-band wireless transceiver and a power management unit retrieving power from a 13.56 MHz carrier through a new 5-coil inductive link. In addition to this SOC, the proposed interface includes a low-power microcontroller, a wideband antenna and a double-sided power recovery coil. All components are bonded on a thin flexible printed circuit board. The AFE uses a new current-reuse circuit topology based on a current-mirror opamp which is scalable to very large number of recording channels, thanks to its small implementation area and its low-power consumption. It includes a low-noise amplifier (LNA) and a programmable gain amplifier (PGA) presenting tree selectable gains of 35 dB, 43.1 dB and 49.5 dB. The SOC is fabricated in a CMOS 180-nm process and has a size of 1.3 mm × 1.8 mm. The AFE has a low-power consumption of 9 µW (4.5 µw for LNA and 4.5 µw for PGA) per channel, for an input referred noise of 3.2 µV. A 5-coil wireless power link is utilized with an efficiency of 28% and a maximum power delivered to the load of 81 mW through a 1 cm2 flexible coil. The ultra wideband edge combining BPSK transmitter reaches a maximum data rate of 800 Mbps at 6.7 pJ/bit, and the 2.4-GHz OOK receiver reaches a maximum data rate of 100 Mbps. The whole system consumes 12.3 mW and weights 0.163 g. Finally, we present biological results obtained in-vivo from the cortex of an anesthetized mouse.