Massimiliano Picca

An overview of logic architectures inside flash memory devices

In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.

Hybrid Storage Systems

In recent years, both industry and academia have increased their research effort in the hybrid memory management space, developing a wide variety of systems. It is worth mentioning that “hybrid” is a generic term and it can have different meanings depending on the context. For instance, a storage system can be hybrid because it combines HDD and SSD; an SSD can be hybrid because it combines SLC, MLC and TLC Flash memories, or it combines NAND with Storage Class Memories (SCMs), which are non-volatile memories like ReRAM, PCM or MRAM. In this chapter we look at all these different meanings. The last section covers over-provisioning and the Write Amplification Factor (WAF): these parameters have a great impact on SSD performances and reliability, as well as on the available storage capacity.

An Isolated Quasi-Resonant Multiphase Single-Stage Topology for 48-V VRM Applications

In order to increase the efficiency of modern microprocessors power supplies used in data centers, the 48-V dc distribution bus is gaining growing attention. For such applications, voltage regulation modules (VRMs) are currently obtained using two-stage conversion systems with an intermediate 12-V dc bus. This paper presents an innovative single-stage approach for the 48-V VRM based on a quasi-resonant constant on-time (COT) operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light load conditions. This is a unique advantage, usually not available in the two-stage approach, that is very important in server architectures, where high efficiency is required even at light load conditions. The paper analyses the circuit topology, and proposes a control architecture for fast transient response, including the current sharing capabilities, and a solution for implementing the integrated magnetics. The digital controller has been implemented in 0.16-

Programmable NAND memory

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Method for error control in multilevel cells with configurable number of stored bits

m lithography together with a digital pulse-width-modulation with a 195 ps resolution, and a 40 MS/s, 7-bit ADC. Experimental results show an efficiency of 93.1% for a 250 A, 1.8 V VRM, and of 93.2% for a 102 A, 1.2-V double data rate (DDR) power supply.