Roberto Cardu

Active Electrode IC for EEG and Electrical Impedance Tomography With Continuous Monitoring of Contact Impedance

The IC presented integrates the front-end for EEG and Electrical Impedance Tomography (EIT) acquisition on the electrode, together with electrode-skin contact impedance monitoring and EIT current generation, so as to improve signal quality and integration of the two techniques for brain imaging applications. The electrode size is less than 2 cm2 and only 4 wires connect the electrode to the back-end. The readout circuit is based on a Differential Difference Amplifier and performs single-ended amplification and frequency division multiplexing of the three signals that are sent to the back-end on a single wire which also provides power supply. Since the systems CMRR is a function of each electrodes gain accuracy, an analysis is performed on how this is influenced by mismatches in passive and active components. The circuit is fabricated in 0.35 μm CMOS process and occupies 4 mm2, the readout circuit consumes 360 μW, the input referred noise for bipolar EEG signal acquisition is 0.56 μVRMS between 0.5 and 100 Hz and almost halves if only EEG signal is acquired.

Electrode contact impedance sensitivity to variations in geometry

Electrode contact impedance is a crucial factor in physiological measurements and can be an accuracy-limiting factor when performing electroencephalography and electrical impedance tomography. In this work, standard flat electrodes and micromachined multipoint spiked electrodes are characterized with a finite-element method electromagnetic solver and the dependence of the contact impedance on geometrical factors is explored. It is found that flat electrodes are sensitive to changes in the outer skin layer properties related to hydration and thickness, while spike electrodes are not. The impedance as a function of the effective contact area, number of spikes and penetration depth has also been studied and characterized.

Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wire

The IC presented integrates the front-end for EEG and Electrical Impedance Tomography acquisition on the electrode, together with contact impedance monitoring, so as to improve signal quality and functional integration of the two techniques for brain imaging applications. Only 4 wires connect the electrode to the back-end. The readout circuit consumes 1 mW, while the input referred noise for EEG signal acquisition is 0.45 μVRMS between 0.5 and 100 Hz, doubling when both EEG and EIT are acquired simultaneously.

Input/Output Pad for Direct Contact and Contactless Testing

Non-contact probing can provide an important contribution for testing complex Systems-on-a-Chip (SoC), Systems-in-a-Package (SiP) and Through-Silicon-Vias (TSV) interconnections. This paper demonstrates the feasibility of wireless testing by capacitive coupling between a cantilever probe card and a pad. In particular a scheme of an I/O pad suitable for both contact and contactless probing is proposed.

Chip-to-chip communication based on capacitive coupling

This paper presents a review of the solutions proposed for chip-to-chip communication based on capacitive coupling. Circuit designs, assembly options and various different test cases are presented in this work. It is shown that this 3D technology is capable of transferring digital data between two dies at high-speed with low power consumption, and likewise analog signals without the need for any extra-wafer processing. The results presented highlight the key features of capacitive coupling when compared to other 3D interconnections and justify the effort to overcome some open issues and make it a marketable technology.

3D system on chip memory interface based on modeled capacitive coupling interconnections

A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35μW/Gbit/sec and an area occupancy of 0.05mm2.