Massimo Bocchi

XiSystem: a XiRisc-based SoC with a reconfigurable IO module

In the nanometer era, the increase in nonrecurring engineering costs is a challenge for SoCs that can be faced through a standardization process. Hardware specialization of a standard platform to a given application can be achieved by exploiting reconfigurable technology. This paper presents a XiSystem SoC, which integrates two different field-programmable devices to provide application-specific computing blocks and IOs. A XiRisc reconfigurable processor is exploited to achieve more than one order of magnitude speed-up and energy consumption reduction vis-a/spl grave/-vis a DSP-like processor, while an eFPGA is integrated in the system in order to make it flexible enough to support various IO ports and protocols. The reconfigurable IO device is also utilized for pre/post data processing and implementation of some standard computational blocks.

A Multi-Context Pipelined Array for Embedded Systems

The integration of a reconfigurable device into complex SoCs is a common request aimed at adding software programmable efficient computational blocks to a system. In such environment a traditional approach in FPGA design could not meet the need for an easy-to-use and easy-to-integrate device. This paper presents the PiCoGA-II reconfigurable datapath which has been designed as a multi-context array to provide fast dynamic reconfiguration. Architectural choices to reduce the area overhead of this approach are described. A reconfigurable dedicated control unit provides a clear interface for an easy integration of the device together with a hardware support for a programming Mow starting from a sequential high-level language. The logic cells have been redesigned with respect to the previous version, to improve their computational efficiency and flexibility. The PiCoGA-II has been fabricated in 0.13mum CMOS technology. The implementation of several MPEG-2 kernels shows that the multi-context array has a computational density which is 2times higher than an equivalent single-context one and is 2times higher than a Virtex-II FPGA when all the 4 contexts are utilized

A system level IP integration methodology for fast SOC design

In the system-on-chip (SOC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrated IP-reuse methodology in the design flow, in order to speed up the designers productivity. In this paper, a SOC design platform is proposed as a solution to this problem, providing a library of IP reusable blocks and a high level tool for SOC design development. An IP library based on AMBA bus architecture was built, featuring a collection of devices with homogeneous interfaces described with VHDL language constructs that enable hardware configurability. A system-level assembler (SLA) was then developed to provide a hardware configuration tool and a suite of utilities to support the designer work. Once defined the system structure, the SLA allows automatic generation of the environments used for software development, simulation, synthesis and verification tasks.

A XiRisc-based SoC for embedded DSP applications

Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC processor features an extensible instruction set, obtained through dynamic reconfiguration of a programmable gate-array embedded as a processor datapath function unit. A prototype chip has been implemented in 0.13 /spl mu/m CMOS technology. The SoC operates at 166 MHz clock speed and the test of several DSP algorithms showed speed-ups ranging from 5/spl times/ to 80/spl times/ with 65%-95% energy savings. As proof of the architectural improvement, energy and area computational efficiency has grown by a factor ranging from 3/spl times/ to 35/spl times/.

The biocompatibility of materials used in printed circuit board technologies with respect to primary neuronal and K562 cells

Printed circuit board (PCB) technology can be used for producing lab-on-a-chip (LOAC) devices. PCBs are characterized by low production costs and large-scale development, both essential elements in the frame of disposable applications. LOAC platforms have been employed not only for diagnostic and/or analytical purposes, but also for identification and isolation of eukaryotic cells, including cancer and stem cells. Accordingly, the compatibility of the employed materials with the biological system under analysis is critical for the development of LOAC devices to be proposed for efficient and safe cell isolation. In this study, we analyzed the in-vitro compatibility of a large set of materials and surface treatments used for LOAC development and evaluation with quasi-standard PCB processes. Biocompatibility was analyzed on hippocampal primary cells (a model of attached cell cultures), in comparison with the reference K562 cell line (a model of cells growing in suspension). We demonstrate here that some of the materials under study alter survival, organization, morphology and adhesion capacity of hippocampal cells, and inhibit growth and differentiation of K562 cells. Nonetheless, a subset of the materials tested did not negatively affect these functions, thus demonstrating that PCB technology, with some limitations, is suitable for the realization of LOAC devices well compatible at least with these preparations.

A cycle-accurate ISS for a dynamically reconfigurable processor architecture

Reconfigurable processor architectures (RAs) have been proving as an effective way to couple significant performance improvements with severe energy constraints, such as those imposed by modern portable real-time applications. XiRisc is a VLIW RISC processor architecture featuring a reconfigurable dataflow-oriented functional unit, the so-called PiCoGA, allowing run-time dynamic extension of the instruction set. In this paper, we propose a LISA-based instruction set simulator (ISS) for the reconfigurable processor, retargetable through a dynamically linked library that emulates instruction set extension. The ISS comprises a SystemC system-level model with embedded bus architecture and memory hierarchy (on-chip and off-chip) to provide a reconfigurable system-on-chip performance evaluator.

High Yield Patterning of Single Cells from Extremely Small Populations

Many biological assays require the ability to isolate and process single cells. Some research fields, such as the characterization of rare cells, the in vitro processing of stem cells, and the study of early stage cell differentiation, call for the additional and typically unmet ability to work with extremely low-count cell populations. In all these cases, efficient single-cell handling must be matched with the ability to work on a limited number of cells with a low cell loss rate. In this paper, we present a platform combining flow-through processing with deterministic (nonstatistical) patterning of cells coming from extremely small cell populations. We describe here modules using dielectrophoresis to control the position of cells flowing in microchannels and to pattern them in open microwells where cells were further analyzed. K562 cells continuously flowing at a speed of up to 100 μm/s were tridimensionally focused, aligned, and patterned inside microwells. A high-patterning yield and low cell loss rate were demonstrated experimentally: 15uL drops, containing an average of 15 cells, were transferred to the microchannel with an 83% yield, and cells were then patterned into microwells with a 100% yield. The deterministic patterning of cells was demonstrated both by isolating single cells in microwells and by creating clusters composed of a predetermined number of cells. Cell proliferation was assessed by easily recovering cells from open microwells, and a growth rate comparable to the control was obtained.

Electronic Microsystems for Handling of Rare Cells

This review paper summarizes some of the most challenging issues regarding the development of electronic microsystems for the isolation, manipulation, and characterization of rare cells. Two relevant areas, namely, immunology for cancer therapy and monitoring of microbial contaminants in water, are presented as example applications which require handling of rare cells. Starting from these applications, the state of the art in electronic microsystem research is presented, and various solutions are discussed, highlighting the advantages and disadvantages of each technology and suggesting the need to integrate multiple solutions to meet the application requirements.

A case-study on multimedia applications for the XiRisc reconfigurable processor

Embedded real-time multimedia applications pose several challenges in order to satisfy increasing quality of service (QoS) and energy consumption constraints, that are hardly matched by the capabilities of general-purpose standard processors. Reconfigurable processors, coupling the flexibility of software-programmable devices with the computational efficiency of application specific architectures, represent an appealing trade-off for next generation devices in the digital signal processing application domain. In this paper, we present a benchmarking application for the XiRisc reconfigurable processor, based on a public release of the MPEG-2 video encoder. The introduction of the reconfigurable logic gives a 5times performance improvement and a 66% energy saving

A stream register file unit for reconfigurable processors

This paper presents a local buffer memory in the form of a stream register file (SRF) that was developed in order to connect, in a compiler-friendly pattern, large-bandwidth run-time configurable logic units in processor-based SOCs. The proposed SRF offers to the host SOC system performance speedups in the range of 4times, with area/power overhead in the order of 6%. The described hardware and algorithm mapping strategy was implemented on silicon in a SOC based on the PiCoGA reconfigurable architecture. The SOC provides an average 450 MOPS (mega operations per Second) in STM CMOS090 technology running at 100MHZ