Mario Toma

XiSystem: a XiRisc-based SoC with a reconfigurable IO module

In the nanometer era, the increase in nonrecurring engineering costs is a challenge for SoCs that can be faced through a standardization process. Hardware specialization of a standard platform to a given application can be achieved by exploiting reconfigurable technology. This paper presents a XiSystem SoC, which integrates two different field-programmable devices to provide application-specific computing blocks and IOs. A XiRisc reconfigurable processor is exploited to achieve more than one order of magnitude speed-up and energy consumption reduction vis-a/spl grave/-vis a DSP-like processor, while an eFPGA is integrated in the system in order to make it flexible enough to support various IO ports and protocols. The reconfigurable IO device is also utilized for pre/post data processing and implementation of some standard computational blocks.

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as EDGE (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-operability. This paper presents analog and digital base-band circuits that are able to support GSM (with EDGE), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level.

A pipelined configurable gate array for embedded processors

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.

A C-based algorithm development flow for a reconfigurable processor architecture

Reconfigurable processors are an appealing option to achieve high performance and low energy consumption in digital signal processing, but their utilization often involves hardware issues not usual for algorithm developers proficient in high level languages. This paper presents a C-based algorithm development flow for XiRisc, a reconfigurable processor architecture targeted at embedded systems, that couples a VLIW risc core with a custom designed programmable hardware unit optimized for being programmed starting from data flow graph (DFG) descriptions. Starting from C-language, the flow produces both executable codes for the processor core and configuration bits for the embedded programmable unit. The proposed flow was utilized for implementing a set of DSP algorithms on a prototypal 0.18 /spl mu/m XiRisc test-chip obtaining performance speed-ups up to 10x and energy consumption reduction up to 75%.

A dataflow control unit for C-to-configurable pipelines compilation flow

In the field of embedded systems, reconfigurable processors, composed of a standard processor core coupled with a reconfigurable device, are gaining more and more importance. Algorithm developers are facing the issue of mapping applications on configurable hardware, without a specific knowledge of the underlying architecture. In this paper, we present a modular data flow control unit for a reconfigurable datapath, which can be easily programmed starting from the C description of the required functionality.

A reconfigurable processor architecture and software development environment for embedded systems

Flexibility, high computing power and low energy consumption are strong guidelines when designing new generation embedded processors. Traditional architectures are no longer suitable to provide a good compromise among these contradictory implementation requirements. In this paper we present a new reconfigurable processor that tightly couples a VLIW architecture with a configurable unit implementing an additional configurable pipeline. A software development environment is also introduced providing a user-friendly tool for application development and performance simulation. Finally, we show that the HW/SW reconfigurable platform proposed achieves dramatic improvement in both speed and energy consumption on signal processing computation kernels.

A XiRisc-based SoC for embedded DSP applications

Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC processor features an extensible instruction set, obtained through dynamic reconfiguration of a programmable gate-array embedded as a processor datapath function unit. A prototype chip has been implemented in 0.13 /spl mu/m CMOS technology. The SoC operates at 166 MHz clock speed and the test of several DSP algorithms showed speed-ups ranging from 5/spl times/ to 80/spl times/ with 65%-95% energy savings. As proof of the architectural improvement, energy and area computational efficiency has grown by a factor ranging from 3/spl times/ to 35/spl times/.

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW

A case-study on multimedia applications for the XiRisc reconfigurable processor

Embedded real-time multimedia applications pose several challenges in order to satisfy increasing quality of service (QoS) and energy consumption constraints, that are hardly matched by the capabilities of general-purpose standard processors. Reconfigurable processors, coupling the flexibility of software-programmable devices with the computational efficiency of application specific architectures, represent an appealing trade-off for next generation devices in the digital signal processing application domain. In this paper, we present a benchmarking application for the XiRisc reconfigurable processor, based on a public release of the MPEG-2 video encoder. The introduction of the reconfigurable logic gives a 5times performance improvement and a 66% energy saving

Compact Buffered Routing Architecture

In this paper we propose a new routing architecture, based on a new switch called T-switch, which we implement in two different versions. Our approach is based on a modified disjoint topology in order to reduce the number of buffers required and on the introduction of a decoding stage between configuration memories and the switch to reduce the number of SRAM cells. This solution is particularly suitable for multi-context arrays, where configuration memory cells need to be replicated as many times as the number of contexts.