Massimo Pozzoni

Injection-Locked CMOS Frequency Doublers for

On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 μm CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1% tuning range around 115 GHz.

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High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block. Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over >;13 GHz bandwidth, -22.5 dBc integrated phase noise while consuming 84 mW.

-Wave and mm-Wave Applications

Multi-Gb/s wireless communications, allocated in the unlicensed spectrum around 60GHz, have been the topic of intense research in the recent past and devices are expected to hit the market shortly. Key aspects behind the increasing interest for technology deployment are the feasibility of the radio in scaled CMOS and the successful demonstration of Gb/s transmissions [1]. Despite the fact that several circuit techniques at mm-Waves have been introduced in the public literature, key aspects of the analog processing tailored to the application requirements need to be addressed. Four channels covering 57GHz to 66GHz are specified [2]. Considering spreads due to process variation, an ultra-wide RF bandwidth of more than ∼12GHz has to be covered with fine sensitivity. In order to allow high-end rate transmissions, the phase noise of the reference signal is extremely stringent. Furthermore, low power consumption is key to enabling multiple transceivers on the same chip.

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators

This paper presents a fully integrated receiver for mm-wave WLANs comprising LNA, RF mixer, quadrature IF mixers, local oscillator plus output stage for characterization, in 65 nm CMOS. The IF frequency set to 1/3 the RF frequency slides according to the received frequency. The architecture choice allows running the quadrature VCO around 20 GHz. A Phase Noise of −115 dBc/Hz @ 10 MHz offset from an equivalent LO at RF carrier is achieved with 36 mW power consumption and 12.5% frequency tuning range. The design of building blocks is discussed in details. Implemented prototypes use low-power digital devices and other measured performances are: 28 dB peak gain, 9 dB noise figure, 5 GHz RF bandwidth, −26 dBm 1-dB compression point, ≫ 60 dB IRR. Total Power consumption is 80 mW from 1.5 V supply.

A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

Ultra-scaled CMOS devices offer the possibility of operation beyond 100GHz where new applications are envisioned in the near future, including imaging and spectroscopy systems for scientific, medical, space, and industrial applications at low cost, light weight and easy assembly [1]. However, a long path toward complete systems of any commercial interest is required, even though simple building blocks have already been presented [2–6]. One of the challenges of such high-frequency transceivers is the on-chip reference generation. Adoption of a voltage-controlled oscillator (VCO) at fundamental frequency sets an increasingly severe trade-off between high spectral purity and frequency tuning due to a dramatic reduction of resonator quality factor and large parasitics introduced by active devices and buffers, operating close to the transition frequency. As an example, state-of-the-art varactor-tuned VCOs beyond 100GHz in standard CMOS technology display a tuning range of less than 3%, not enough to cover process spreads [3–5]. An alternative solution relies on frequency multiplication of a lower frequency reference, with the potential advantage of a higher tuning range and lower phase noise set by the lower frequency VCO enslaving the multiplier.

A sliding IF receiver for mm-wave WLANs in 65nm CMOS

Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE) and Duobinary (DB) prove to be effective techniques assuring signal integrity in the presence of ISI, but with speed increase the accuracy of the timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery [1][2][3]. DB alternative may suffer in the presence of long sequences of incoming toggle patterns (1010…). In fact, in DB the channel frequency response is pre-shaped into a target shape, but toggle patterns are converted into a constant level, thus not providing information to the timing loop [2][4].

A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization

A 65 nm CMOS receiver including a tapered chain linear equalization and a mixer based clock recovery circuit capable of SSC tracking is presented. The proposed architecture works up to 10 Gb/s with transmission channels with more than 20 dB loss at Nyquist, while consuming 110 mA and occupying 0.25 mm2.

A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies