Matt Kucic

A programmable continuous-time floating-gate Fourier processor

We present a programmable continuous-time floating-gate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolatile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a weight and then computing an inverse PFT. We decompose the frequency bands of the incoming signal using the transistor-only version of the autozeroing floating-gate amplifier (AFGA), also termed the capacitively coupled current conveyer (C/sup 4/). Each band decomposition is then fed through a floating-gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using Kirchoff current law to give a band-weighted output of the original signal. We examine many options to reduce second-order harmonic problems inherent in the single-sided C/sup 4/. We present a method for programming arrays of floating-gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor.

Programmable and adaptive analog filters using arrays of floating-gate circuits

In this paper we describe a programmable and adaptive filter based on floating-gate technology We review the basics of floating-gate techniques and how they enable programmable and adaptive filter circuits. We describe our programmable filter concepts, and show experimental results of programmable filter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further, we describe our techniques and custom programmer board for floating-gate programming of an IC. We show how to extend our programmable filters as adaptive filters both through weight perturbation methods and continuously adapting correlation rule methods.

Accurate programming of analog floating-gate arrays

This paper presents an accurate method for programming analog values into an array of floating-gate pFETs. Channel hot-electron (CHE) injection is used to program the devices and the programming algorithm is based upon a representation of the physical injection equation. The programming accuracy is dependent upon the physical parameters fitting of this equation and the algorithm updates these physical parameters to correspond with the current region of operation. The control circuits used to access each element and program the array are contained on a custom programming board which interfaces to a computer via a serial connection.

Mel-frequency cepstrum encoding in analog floating-gate circuitry

This paper presents a continuous-time mel-frequency cepstrum encoding IC using analog circuits and floating-gate computational arrays. We present the dynamics of several floating-gate computational building blocks and accompanying experimental measurements. We also present a novel approach to programmable signal spectrum decomposition, analog frequency transforms, and spectrum compaction. Experimental data is presented from circuits fabricated on a 0.5 /spl mu/m nwell CMOS process available through MOSIS. This system can act as the front-end for larger digital or analog speech processing systems.

A transistor-only circuit model of the autozeroing floating-gate amplifier

We developed an transistor-only version of our autozeroing floating-gate amplifier (AFGA). We use a subthreshold transistor to model the behavior of an electron-tunneling device, and we use another subthreshold transistor to model the behavior of pFET hot-electron injection. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data. This circuit is a bandpass filter, and behaves similarly to the AFGA with different operating parameters. Both the low-frequency and high-frequency cutoffs are controlled electronically, as is done in continuous-time filters. This circuit has a low-frequency cutoff at frequencies above 1 Hz, and therefore complements the operating regimes of the AFGA.

Characterization of charge-pump rectifiers for standard submicron CMOS processes

This work presents an innovative approach in designing CMOS charge pumps for a 0.6 /spl mu/m CMOS process for the control of floating-gate circuits. Central to this design are rectifier structures which would function best for both medium and high voltage applications. Shown in this paper are six different rectifier structures designed and fabricated in a standard 0.6 /spl mu/m CMOS n-well double poly process along with experimental results. These rectifiers structures are then implemented in two stage Dickson charge pumps in a standard 0.6 /spl mu/m CMOS process to determine their effectiveness. Experimental results show by way of comparison charge pump performance with the experimental results of the rectifying structures.

A programmable continuous-time analog Fourier processor based on floating-gate devices

We present a programmable continuous-time floating-gate Fourier processor that decomposes the frequency bands using analog bandpass filters, multiplies each channel by a non-volatile weight, and then recombines the frequency channels. A DSP would take a similar approach of computing a FFT, multiplying the frequency components by a weight, then computing an inverse FFT. We decompose the frequency bands of an incoming signal using the transistor only circuit model of the Autozeroing Floating-Gate Amplifier (AFGA) or also termed C4 (Capacitivly Coupled Current Conveyer). Each band decomposition is then fed through a floating gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using KCL to give a band weighted output of the original signal. We examine many options to reduce 2nd order harmonic problems inherent in the single sided C4. We present a method for programming arrays of floating gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor.

Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuits

This paper presents integration of high voltage charge-pumps for programming analog floating-gate (FG) circuits in a standard 0.5 /spl mu/m CMOS N-well double poly process. In this research two different Dickson charge-pumps are integrated for the control of electron tunneling and hot-electron injection in a floating-gate element. A six stage design implemented with Schottky rectifiers is used to modulate tunneling and a three stage design using high voltage transistors is used to modulate injection. Controlling the frequency of the Schottky charge-pump is an on-chip clock. The on-chip clock, a 7 stage ring oscillator was designed to operate to approximately 10 MHz for controlling the Schottky charge-pump. Experimental results of hot-electron injection, clock performance and electron tunneling are presented.

On-chip analog floating-gate array programming in a submicron standard CMOS process using high voltage charge pumps

This paper presents a novel design of on-chip programming for floating-gate arrays in a 0.5 /spl mu/m standard CMOS N-well double poly process. Described in this paper is the complete design for integrating on chip the floating-gate programming infrastructure for programming a 10/spl times/10 array: electron injection and tunneling charge pumps, on-chip clock, and all interfacing circuitry to the array and pads. The three stage high voltage charge pump (HVCP) is utilized to modulate electron injection and six stage Schottky charge pumps (SCHCP) are utilized to modulate tunneling. Experimental results of hot-electron injection and electron tunneling for a floating-gate element are presented as well as simulation results for the critical interfacing circuitry and for the on-chip clock.

5V-only, standard 0.5/spl mu/m CMOS programmable and adaptive floating-gate circuits and arrays using CMOS charge pumps

This work presents the integration of high voltage charge pumps into floating-gate arrays in a standard 0.5/spl mu/m CMOS n-well double poly process. In this research two different Dickson charge pumps are presented for the tunnelling and injection in floating-gate circuits and arrays. A six stage design implemented with Schottky rectifiers is used to modulate tunneling and a three stage high voltage design is used to modulate injection. The Schottky configuration is able to boost the output voltage to approximately 18V while sourcing 1/spl mu/A and the high voltage configuration is able to boost the output voltage to approximately 7V while sourcing 0.1/spl mu/A. In both cases no voltage skipping is observed in the output voltage. Experimental results and analysis of each configuration are presented.