Jeff Dugger

Programmable and adaptive analog filters using arrays of floating-gate circuits

In this paper we describe a programmable and adaptive filter based on floating-gate technology We review the basics of floating-gate techniques and how they enable programmable and adaptive filter circuits. We describe our programmable filter concepts, and show experimental results of programmable filter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further, we describe our techniques and custom programmer board for floating-gate programming of an IC. We show how to extend our programmable filters as adaptive filters both through weight perturbation methods and continuously adapting correlation rule methods.

An analog floating-gate node for Supervised learning

We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible.

A floating-gate vector-quantizer

We present a floating-gate based system for computing vector quantization (VQ), which is typically used for data compression and classification of signals to symbols. We present an architecture and resulting circuits which will enable direct programming/storage of weight vectors, as well as methods for adaptive VQ. We use an analog bump circuit to perform a continuous distance computation along a particular input coordinate. Unlike a traditional bump circuit, we use differential floating-gate inputs to provide the ability to store the learned value. The current outputs of each bump circuit are summed along a single wire, where the largest result(s) are selected using a winner-take-all circuit. We present experimental results measured from ICs fabricated on a 0.5 /spl mu/m CMOS process available through MOSIS.

An adaptive analog synapse circuit that implements the least-mean-square learning rule

In this paper a compact adaptive analog synapse circuit that implements the least-mean-square (LMS) learning rule is described. Basic simulation results demonstrate the LMS learning rule in the proposed circuit. An adaptive linear combiner that uses the proposed synapse is shown to learn a square wave that matches closely with the desired target. Issues of weight decay and its implications to the design of the synapse circuit are presented as well. The synapse is designed in a 0.5 /spl mu/m CMOS technology.

Improved correlation learning rule in continuously adapting floating-gate arrays using logarithmic pre-distortion of input and learning signals

Floating-gate pFETs can be used to implement analog signal multiplication with an adaptive analog gain, creating the possibility for compact, low-power analog adaptive filters and neural networks in VLSI. We have shown that the adaptation mechanism of this device yields a weight which is proportional to correlations between terminal voltage signals. However, the weight contains dependencies proportional to the variances of these terminal voltages as well. In addition, harmonic distortion of the input signals can mask thin correlation effect. In this paper we show how to eliminate or minimize these non-idealities through logarithmic pre-distortion of our input and learning signals as well as through the use of differential circuit structures. The result is a weight update mechanism which is closer to a pure correlation learning rule.

Supervised learning in a two-input analog floating-gate node

We pursue the realization of on-chip supervised learning networks for large-scale, real-time signal processing applications using array of analog floating-gate synapses. We present experimental data characterizing the performance of a two-input analog floating-gate pFET synapse network that implements a supervised learning algorithm similar to the least-mean square (LMS) learning rule; most other supervised learning algorithm possess a straight-forward relation to the LMS algorithm. Analog floating-gate synapses enable larger-sale, on-chip learning networks than previously possible.

An analog adaptive beamforming circuit for audio noise reduction

We have designed and built the first commercially available all-analog adaptive beamforming integrated circuit utilizing a dual microphone array. Beamforming performs spatial filtering by exploiting time-of-arrival differences between microphones. Our analog implementation has the advantage of using very little power which is important in portable, battery-powered devices. Rather than optimize parameters for a single filter as in a standard adaptive FIR filter used in conventional beamformers, our implementation selects among multiple filters each pre-programmed to provide various different spatial-filter patterns.

A continuously-adapting analog node using floating-gate synapses

Demonstrates that a network of pFET single-transistor learning synapses implements a multi-input adaptive node. These floating-gate synapses are capable of four-quadrant multiplications between an input and a weight, as well as adapting to a four-quadrant correlation between the input and a learning signal applied as a drain voltage. Our adaptive floating-gate node structure converges to the correct solution for constant RMS input values during adaptation. Our structure accounts for device mismatch, gate variance, and drain variance effects in the learning rule. We present experimental results for our circuit.

A supervised neural network layer of continuously adapting, analog floating-gate nodes

We present an LMS node based upon an improved continuously adapting, analog floating-gate synapse that exhibits minimal weight decay. Our approach is based upon a recently developed synapse element based upon our tradition on single-transistor learning synapses with minimal weight decay. We show the transition from a single floating-gate synapse element to a single floating-gate node, demonstrated using results from simple LMS experiments. We present experimental data from ICs fabricated in 0.5 /spl mu/m CMOS process.