Matt Malloy

Technology review and assessment of nanoimprint lithography for semiconductor and patterned media manufacturing

The semiconductor and hard disk drive industries are investigating nanoimprint for future high volume manufacturing of memory devices and patterned media. Nanoimprint, a form of 1× contact lithography, is one of the few technologies capable of meeting the resolution requirements for next generation electronic and storage devices. Its ability to produce small features with low line width roughness and critical dimension uniformity has been demonstrated by multiple sources. Significant improvements in defectivity have been shown; overlay has improved to within a factor of 2 of that required by the International Technology Roadmap for Semiconductors for 22 nm node flash memory devices; and next generation tools, templates, and processes are being commercialized and tested at end-user sites. Defectivity, throughput, and infrastructure remain as critical challenges, but each has experienced marked improvements in the past year. This technology review and assessment covers critical aspects of nanoimprint for both semiconductor and patterned media manufacturing. It focuses on jet and flash imprint lithography, the type of nanoimprint most often considered for these two applications. The requirements and current status of nanoimprint with respect to high volume manufacturing are presented, and critical aspects are discussed.

Photons, electrons, and acid yields in EUV photoresists: a progress report

This paper describes our initial investigation into building a greater understanding of the complex mechanism occurring during extreme ultraviolet (EUV) exposure of resist materials. In particular, we are focusing on the number and energy of photoelectrons generated and available for reaction with photoacid generators (PAGs). We propose that this approach will best enable the industry to develop resists capable of meeting resolution, line width roughness (LWR), and sensitivity requirements.

Step and flash imprint lithography for semiconductor high volume manufacturing

Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. However, many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for semiconductor high volume manufacturing (HVM). This paper discusses the current status of SFIL, including the process and templates, and shows where more industry collaboration is needed to solve the most critical issues.

Further advancing the throughput of a multi-beam SEM

Multiple electron beam SEMs enable detecting structures of few nanometer in diameter at much higher throughputs than possible with single beam electron microscopes at comparable electron probe parameters. Although recent multiple beam SEM development has already demonstrated a large speed increase1, higher throughputs are still required to match the needs of many semiconductor applications2. We demonstrate the next step in the development of multi-beam SEMs by increasing the number of beams and the current per beam. The modularity of the multi-beam concept ensures that design changes in the multi-beam SEM are minimized.

SEMATECH's nanoImprint program: a key enabler for nanoimprint introduction

SEMATECH has initiated a nanoimprint program and started imaging experiments with a Molecular Imprints Imprio300TM system at the SEMATECH facility in Albany, NY. An overview of the SEMATECH nanoimprint development program is presented as well as an assessment of nanoimprint technology strengths and weaknesses. SEMATECH plans to explore many of the critical aspects of the nanoimprint process to drive key improvements in overlay, imprint mask cleaning, and defectivity toward making nanoimprint technology a cost-effective lithography strategy for CMOS development and manufacturing applications. Results of nanoimprint overlay with a previous level exposed on a 1.35NA immersion lithography scanner show it has noticeably improved over previous results with champion data in the 18nm range. Imprint mask cleaning on an automated tool has shown no measurable degradation of critical dimension or line width roughness after ten cleaning cycles.

Assessing the viability of multi-electron beam wafer inspection for sub-20nm defects

SEMATECH has initiated a program to accelerate the development and commercialization of multi-electron beam based technologies as successor for wafer defect inspection in high volume semiconductor manufacturing. This paper develops the basic electron-optical performance requirements and establishes criteria for tool specifications. The performance variations within a large array of electron beams must be minimal in order to maximize defect capture rates while simultaneously minimizing false counts, so a series of experimental evaluations are described to quantify the random and systematic variations in beam current, spot size, detector channel noise level, and defect sensitivity.

Jet and flash imprint defectivity: assessment and reduction for semiconductor applications

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprints ability to meet defect requirements originates in part from the industrys past experiences with 1X lithography and the shortage in end-user generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECHs defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm.

Massively parallel E-beam inspection: enabling next-generation patterned defect inspection for wafer and mask manufacturing

SEMATECH aims to identify and enable disruptive technologies to meet the ever-increasing demands of semiconductor high volume manufacturing (HVM). As such, a program was initiated in 2012 focused on high-speed e-beam defect inspection as a complement, and eventual successor, to bright field optical patterned defect inspection [1]. The primary goal is to enable a new technology to overcome the key gaps that are limiting modern day inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. The program specifically targets revolutionary solutions based on massively parallel e-beam technologies, as opposed to incremental improvements to existing e-beam and optical inspection platforms. Wafer inspection is the primary target, but attention is also being paid to next generation mask inspection. During the first phase of the multi-year program multiple technologies were reviewed, a down-selection was made to the top candidates, and evaluations began on proof of concept systems. A champion technology has been selected and as of late 2014 the program has begun to move into the core technology maturation phase in order to enable eventual commercialization of an HVM system. Performance data from early proof of concept systems will be shown along with roadmaps to achieving HVM performance. SEMATECH’s vision for moving from early-stage development to commercialization will be shown, including plans for development with industry leading technology providers.

Actinic review of EUV masks: Status and recent results of the AIMS EUV system

The EUV mask infrastructure is of key importance for the successful introduction of EUV lithography into volume production. In particular, for the production of defect free masks an actinic review of potential defect sites is required. To realize such an actinic review tool, Carl Zeiss and the SEMATECH EUVL Mask Infrastructure consortium started a development program for an EUV aerial image metrology system, the AIMS™ EUV. In this paper, we discuss the current status of the prototype integration and show recent results.

Enabling future generation high-speed inspection through a massively parallel e-beam approach

New device architectures and materials are being introduced to develop 10 and 7 nm node manufacturing processes. In addition, the increasing complexity of multiple patterning adds significant yield challenges. The critical metrology challenges for yield assurance include defect control, control of critical dimension and critical dimension uniformity, and pattern placement control. To support the industry in meeting those challenges SEMATECH continues to evaluate new disruptive metrology technologies that can meet the requirements for high volume manufacturing (HVM). High-speed massively parallel e-beam defect inspection has the potential to address the key gaps limiting todays patterned defect inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. While SEMATECH targets patterned defect inspection first, the technology also has the potential to support the increasing number of hot spot inspection requirements related to critical dimension uniformity and pattern placement that come with self-aligned quadruple patterning. In addition to wafer applications, next generation mask inspection will benefit from a faster high resolution inspection technology. In late 2014 SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for patterned wafer inspection. The selection of a champion technology was made and a core technology maturation phase started with the goal of enabling the eventual commercialization of an HVM system. This paper begins with a brief overview of the industry need and the program being developed to address it. Key technical topics pertaining to imaging performance and defect sensitivity are then examined. Performance data from early proof of concept systems will be shown. The capabilities in development to accurately access defect sensitivity using the core technology will be discussed, and initial results for two types of samples will be provided. Development towards the next generation of non-proprietary test samples will also be presented.