Matthew C. Graf

Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time. An additional benefit is the ease of testing intercomponent connections.

Method of concurrently testing each of a plurality of interconnected integrated circuit chips

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time. An additional benefit is the ease of testing intercomponent connections.

Decomposition-aware standard cell design flows to enable double-patterning technology

Maintaining the microelectronics industrys aggressive pace of density scaling beyond the resolution limits of optical lithography is forcing the introduction of double-patterning technology (DPT) that effectively doubles the pattern density achievable with 193nm optical lithography. This paper investigates the degree to which DPT affects design tools, layout methodologies, and data standards. Design solutions are demonstrated and the efficiency of various double-patterning aware design methodologies is compared based on the first metal level of a 20nm-node standard cell design flow. Necessary design-tool and data-standard requirements for a DPT-aware standard cell design flows are enumerated and summarized.

IBM Enterprise System/900 Type 9121 Model 320 air-cooled processor technology

The basic component of the new IBM Enterprise System/9000™ Type 9121 Model 320 processor is an air-cooled thermal conduction module (TCM). The fabrication of this module required the integration of new bipolar chips, CMOS SRAM chips, and ECL and DCS logic circuitry in a TCM that could dissipate heat by means of air cooling. The method and details of this process of integration are described and discussed.

Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI

This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.

IBM ES/9000 model 320 air cooled computer technology

The authors describe the IBM ES/9000 model 320, an air-cooled mainframe business computer with engineering and scientific processor features equivalent to those of a water-cooled multiframe IBM system 3090 packaged in a single frame. The key is the technology integration of bipolar logic chips with differential current switch circuits and CMOS static random access memory array chips on a thermal conduction module.<<ETX>>