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Dive into the research topics where Matthew C. Merten is active.

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Featured researches published by Matthew C. Merten.


international solid-state circuits conference | 2014

5.9 Haswell: A family of IA 22nm processors

Nasser A. Kurd; Muntaquim Chowdhury; Edward A. Burton; Thomas P. Thomas; Christopher P. Mozak; Brent R. Boswell; Manoj B. Lal; Anant Deval; Jonathan P. Douglas; Mahmoud Elassal; Ankireddy Nalamalpu; Timothy M. Wilson; Matthew C. Merten; Srinivas Chennupaty; Wilfred Gomes; Rajesh Kumar

The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary goals for the Haswell program are platform integration and low power to enable smaller form factors. Haswell incorporates several building blocks, including: platform controller hubs (PCHs), memory, CPU, graphics and media processing engines, thus creating a portfolio of product segments from fan-less Ultrabooks™ to high-performance desktop, as shown in Fig. 5.9.1. It also integrates a number of new technologies: a fully integrated voltage regulator (VR) consolidating 5 platform VRs down to 1, on-die eDRAM cache for improved graphics performance, lower-power states, optimized IO interfaces, an Intel AVX2 instruction set that supports floating-point multiply-add (FMA), and 256b SIMD integer achieving 2× the number of floating-point and integer operations over its predecessor. The 22nm process is optimized for Haswell and includes 11 metal layers (2 additional metal layers vs. Ivy Bridge [2]), high-density metal-insulator-metal (MIM) capacitors, and is tuned for different leakage/speed targets based on the market segment. For example, in some low-power products, the process is optimized to reduce leakage by 75% at Vmin, while paying only 12% intrinsic device degradation at the high-voltage corner.


Archive | 2004

Compare and exchange operation using sleep-wakeup mechanism

Bratin Saha; Matthew C. Merten; Per Hammarlund


Archive | 2005

Method and apparatus for speculative execution of uncontended lock instructions

Bratin Saha; Matthew C. Merten; Per Hammarlund


Archive | 2015

Method, apparatus, and system for speculative abort control mechanisms

Martin G. Dixon; Ravi Rajwar; Konrad K. Lai; Robert S. Chappell; Rajesh S. Parthasarathy; Alexandre J. Farcy; Ilhyun Kim; Prakash Math; Matthew C. Merten; Vijaykumar B. Kadgi


Archive | 2005

Forward-pass dead instruction identification

Stephan J. Jourdan; Matthew C. Merten; Alexandre J. Farcy


Archive | 2004

Predicting contention in a processor

Bratin Saha; Matthew C. Merten; Sebastien Hily; David A. Koufaty; Per Hammarlund


Archive | 2010

Providing thread fairness in a hyper-threaded microprocessor

Morris Marden; Matthew C. Merten; Alexandre J. Farcy; Avinash Sodani; James D. Hadley; Ilhyun Kim


Archive | 2006

Managing multiple threads in a single pipeline

Matthew C. Merten; Avinash Sodani; James D. Hadley; Alexandre J. Farcy; Iredamola Dammy Olopade


Archive | 2012

Scheduler Implementing Dependency Matrix Having Restricted Entries

Srikanth T. Srinivasan; Matthew C. Merten; Bambang Sutanto; Rahul R. Kulkarni; Justin M. Deinlein; James D. Hadley


Archive | 2015

Instruction and logic to test transactional execution status

Ravi Rajwar; Bret L. Toll; Konrad K. Lai; Matthew C. Merten; Martin G. Dixon

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