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Dive into the research topics where Matthew C. Robbins is active.

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Featured researches published by Matthew C. Robbins.


IEEE Electron Device Letters | 2015

Black Phosphorus p-MOSFETs With 7-nm HfO 2 Gate Dielectric and Low Contact Resistance

Nazila Haratipour; Matthew C. Robbins; Steven J. Koester

We report record contact resistance and transconductance in locally back-gated black phosphorus p-MOSFETs with 7-nm thick HfO<sub>2</sub> gate dielectrics. Devices with effective gate lengths, L<sub>eff</sub>, from 0.55 to 0.17 μm were characterized and shown to have contact resistance values as low as 1.14 ± 0.05 Q-mm. In addition, devices with L<sub>eff</sub> = 0.17 μm displayed extrinsic transconductance exceeding 250 μS/μm and ON-state current approaching 300 μA/μm.


Journal of Vacuum Science and Technology | 2015

Atomic and electronic structure of exfoliated black phosphorus

Ryan J. Wu; Mehmet Topsakal; Tony Low; Matthew C. Robbins; Nazila Haratipour; Jong Seok Jeong; Renata M. Wentzcovitch; Steven J. Koester; K. Andre Mkhoyan

Black phosphorus, a layered two-dimensional crystal with tunable electronic properties and high hole mobility, is quickly emerging as a promising candidate for future electronic and photonic devices. Although theoretical studies using ab initio calculations have tried to predict its atomic and electronic structure, uncertainty in its fundamental properties due to a lack of clear experimental evidence continues to stymie our full understanding and application of this novel material. In this work, aberration-corrected scanning transmission electron microscopy and ab initio calculations are used to study the crystal structure of few-layer black phosphorus. Directly interpretable annular dark-field images provide a three-dimensional atomic-resolution view of this layered material in which its stacking order and all three lattice parameters can be unambiguously identified. In addition, electron energy-loss spectroscopy (EELS) is used to measure the conduction band density of states of black phosphorus, which agrees well with the results of density functional theory calculations performed for the experimentally determined crystal. Furthermore, experimental EELS measurements of interband transitions and surface plasmon excitations are also consistent with simulated results. Finally, the effects of oxidation on both the atomic and electronic structure of black phosphorus are analyzed to explain observed device degradation. The transformation of black phosphorus into amorphous PO3 or H3PO3 during oxidation may ultimately be responsible for the degradation of devices exposed to atmosphere over time.


arXiv: Mesoscale and Nanoscale Physics | 2016

Symmetric Complementary Logic Inverter Using Integrated Black Phosphorus and MoS2 Transistors

Yang Su; Chaitanya U. Kshirsagar; Matthew C. Robbins; Nazila Haratipour; Steven J. Koester

The operation of an integrated two-dimensional complementary metal-oxide-semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET fabricated using a common local backgate electrode with thin (20 nm) HfO2 gate dielectric. The constituent devices have linear threshold voltages of -0.8 V and +0.8 V and produce peak transconductances of 16 uS/um and 41 uS/um for the MoS2 n-MOSFET and BP p-MOSFET, respectively. The inverter shows a voltage gain of 3.5 at a supply voltage, VDD = 2.5 V, and has peak switching current of 108 uA and off-state current of 8.4 uA (2.4 uA) at VIN = 0 (VIN = 2.5 V). In addition, the inverter has voltage gain greater than unity for VDD > 0.5 V, has open butterfly curves for VDD > 1 V, and achieves static noise margin over 500 mV at VDD = 2.5 V. The voltage gain was found to be insensitive to temperature between 270 K and 340 K, and AC large and small-signal operation was demonstrated at frequencies up to 100 kHz. The demonstration of a complementary 2D inverter which operates in a symmetric voltage window suitable for driving a subsequent logic stage is a significant step forward in developing practical applications for devices based upon 2D materials.


Applied Physics Letters | 2015

Determination of the Schottky barrier height of ferromagnetic contacts to few-layer phosphorene

Yoska Anugrah; Matthew C. Robbins; P. A. Crowell; Steven J. Koester

Phosphorene, the 2D analogue of black phosphorus, is a promising material for studying spin transport due to its low spin-orbit coupling and its ½ nuclear spin, which could allow the study of hyperfine effects. In this work, the properties of permalloy (Py) and cobalt (Co) contacts to few-layer phosphorene are presented. The Schottky barrier height was extracted and determined as a function of gate bias. Flat-band barrier heights, relative to the valence band edge, of 110 meV and 200 meV were determined for Py and Co, respectively. These results are important for future studies of spin transport in phosphorene.


ACS Nano | 2016

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents.

Chaitanya U. Kshirsagar; Weichao Xu; Yang Su; Matthew C. Robbins; Chris H. Kim; Steven J. Koester

Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/μm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/μm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.


ACS Applied Materials & Interfaces | 2017

Cyclical Thinning of Black Phosphorus with High Spatial Resolution for Heterostructure Devices

Matthew C. Robbins; Seon Namgung; Sang Hyun Oh; Steven J. Koester

A high spatial resolution, cyclical thinning method for realizing black phosphorus (BP) heterostructures is reported. This process utilizes a cyclic technique involving BP surface oxidation and vacuum annealing to create BP flakes as thin as 1.6 nm. The process also utilizes a spatially patternable mask created by evaporating Al that oxidizes to form Al2O3, which stabilizes the unetched BP regions and enables the formation of lateral heterostructures with spatial resolution as small as 150 nm. This thinning/patterning technique has also been used to create the first-ever lateral heterostructure BP metal oxide semiconductor field-effect transistor (MOSFET), in which half of a BP flake was thinned in order to increase its band gap. This heterostructure MOSFET showed an ON/OFF current ratio improvement of 1000× compared to homojunction MOSFETs.


device research conference | 2015

Integrated MoS 2 n-MOSFETs and black phosphorus p-MOSFETs with HfO 2 dielectrics and local backgate electrodes

Yang Su; Nazila Haratipour; Matthew C. Robbins; Chaitanya U. Kshirsagar; Steven J. Koester

Two-dimensional (2D) semiconductors are of interest for numerous device applications, as they can provide excellent scalability and ease of integration onto arbitrary substrates and high performance transistors have been demonstrated with various 2D materials [1-2]. In particular, MoS2 and black phosphorus (BP) are both promising 2D materials for use in metal-oxide-semiconductor field-effect transistors (MOSFETs). MoS2 is particularly useful for n-MOSFETs [3], but p-type MoS2 devices are difficult to fabricate. On the other hand, recent reports of BP p-MOSFETs have shown excellent performance [4]. However, the only reports of logic circuits based upon material combination have utilized devices with Al2O3 dielectrics [5]. In this paper, we report the co-integration of black phosphorus n-MOSFETs with BP p-MOSFETs using local backgates with high-K HfO2 dielectrics and demonstrate their operation both before and after passivation to create air-stable devices. The devices show high transconductance and excellent matching between p- and n-FET characteristics, and these results pave the way for creating high-performance logic circuits using 2D semiconducting materials.


device research conference | 2015

Black phosphorus n-MOSFETs with record transconductance

Nazila Haratipour; Matthew C. Robbins; Steven J. Koester

Two-dimensional (2D) materials have attracted a great deal of attention for use in a variety of electronic and photonic applications. The layered crystal structure in these materials offers an ultra-thin or even monolayer body thickness, which could reduce short channel effects allowing improved transistor scaling compared to conventional bulk materials. In order to use these 2D materials in complementary logic circuits, it would be desirable to have high performance p-FETs and n-FETs made using the same semiconductor channel. Transition metal dichalcogenides (TMDs) are the most widely studied 2D materials and inverters based on these materials have already been reported. Although these inverters show high voltage gain, their performance is eventually limited by the low mobility in these materials. Recently, the 2D material black phosphorus (BP) has been studied which promises improved performance due to its high electron and hole mobility and thickness-dependent band gap. However, black phosphorus tends to be naturally p-type, and while high-performance BP p-FETs have been demonstrated, achieving high-performance n-FETs has proven to be difficult. In this work, we report Al2O3-passivated black phosphorus n-FETs with record transconductance of 45 μS/μm, a value that is over 10 times higher than the previous best values. These result suggest strong evidence that black phosphorus is a promising material for 2D CMOS applications.


ACS Applied Materials & Interfaces | 2018

Depletion Mode MOSFET Using La-Doped BaSnO3 as a Channel Material

Jin Yue; Abhinav Prakash; Matthew C. Robbins; Steven J. Koester; Bharat Jalan

The high room-temperature mobility that can be achieved in BaSnO3 has created significant excitement for its use as channel material in all-perovskite-based transistor devices such as ferroelectric field effect transistor (FET). Here, we report on the first demonstration of n-type depletion-mode FET using hybrid molecular beam epitaxy grown La-doped BaSnO3 as a channel material. The devices utilize a heterostructure metal-oxide semiconductor FET (MOSFET) design that includes an epitaxial SrTiO3 barrier layer capped with a thin layer of HfO2 used as a gate dielectric. A field-effect mobility of ∼70 cm2 V-1 s-1, a record high transconductance value of >2mS/mm at room temperature, and the on/off ratio exceeding 107 at 77 K were obtained. Using temperature- and frequency-dependent transport measurements, we quantify the impact of the conduction band offset at the BaSnO3/SrTiO3 interface as well as bulk and interface traps on device characteristics.


international electron devices meeting | 2017

Crystal-oriented black phosphorus TFETs with strong band-to-band-tunneling anisotropy and subthreshold slope nearing the thermionic limit

Matthew C. Robbins; Steven J. Koester

We present black phosphorus (BP) TFETs with transport directions aligned to the armchair and zigzag crystal orientations of a 9 nm BP channel fabricated using a triple-gate device structure. Strong (∼104) band-to-band-tunneling anisotropy is observed between the two crystal orientations. Furthermore, we observe a subthreshold slope nearing the thermionic limit of 22 mV/dec at 110 K, a step towards realizing subthermionic SS in BP-TFETs.

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Yang Su

University of Minnesota

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Bharat Jalan

University of Minnesota

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Chris H. Kim

University of Minnesota

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Jin Yue

University of Minnesota

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