Steven J. Koester

Waveguide-integrated black phosphorus photodetector with high responsivity and low dark current

A gated multilayer black phosphorus photodetector integrated on a silicon photonic waveguide operating in the telecom band is demonstrated with intrinsic responsivity up to 135 mA W−1 and 657 mA W−1 in 11.5-nm- and 100-nm-thick devices, respectively.

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

Interconnects in the third dimension: design challenges for 3D ICs

Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two- dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

Strained Si NMOSFETs for high performance CMOS technology

Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.

Practical Strategies for Power-Efficient Computing Technologies

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

High-speed Germanium-on-SOI lateral PIN photodiodes

We report the fabrication and characterization of high-speed germanium on silicon-on-insulator lateral PIN photodetectors. At an incident wavelength of 850 nm, 10 /spl times/10-/spl mu/m detectors with finger spacing S of 0.4 /spl mu/m (0.6 /spl mu/m) produced a -3-dB bandwidth of 29 GHz (27 GHz) at a bias voltage of -1 V. The detectors with S=0.6 /spl mu/m had external quantum efficiency of 34% at 850 nm and 46% at 900 nm and dark current of 0.02 /spl mu/A at -1-V bias.

Wafer-level 3D integration technology

An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

Hafnium oxide gate dielectrics on sulfur-passivated germanium

Sulfur passivation of Ge(100) is achieved using aqueous ammonium sulfide (NH4)2S(aq). The passivation layer is largely preserved after atomic layer deposition of the high-κ dielectric material HfO2 when sufficiently low growth temperatures (e.g., 220°C) are employed. Oxygen incorporation is moderate and results in an electrically passivating GeOS interface layer. The HfO2∕GeOS∕Ge gate stack exhibits lower fixed charge and interface state density than a more conventional HfO2∕GeON∕Ge gate stack fabricated via an ammonia gas treatment.

Optical absorption in graphene integrated on silicon waveguides

To fully utilize graphenes remarkable optical properties for optoelectronic applications, it needs to be integrated in planar photonic systems. Here, we demonstrate integration of graphene on silicon photonic circuits and precise measurement of the optical absorption coefficient in a graphene/waveguide hybrid structure. A method based on Mach-Zehnder interferometry is employed to achieve high measurement precision and consistency, yielding a maximal value of absorption coefficient of 0.2 dB/μm when graphene is located directly on top of the waveguide. The averaged results obtained from a large number of samples agree with theoretical model utilizing the universal ac conductivity in graphene. Our work provides an important guide for the design and optimization of integrated graphene optoelectronic devices.