Matthew Fojtik

Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells

Sensors with long lifetimes create new applications in medical, infrastructure and environmental monitoring. Due to volume constraints, sensor systems are often capable of storing only small amounts of energy. Several systems have increased lifetime through VDD scaling [1][2][3]. This necessitates voltage conversion from higher-voltage storage elements, such as batteries and fuel cells. Power is reduced by introducing ultra-low-power sleep modes during idle periods. Sensor lifetime can be further extended by harvesting from solar, vibrational and thermal energy. Since the availability of harvested energy is sporadic, it must be detected and stored. Harvesting sources often do not provide suitable voltage levels, so DC-DC up-conversion is required.

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction

We propose Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows. A local stalling technique that can be automatically inserted into any design allows the system to scale to larger processors. We implemented Bubble Razor on an ARM Cortex-M3 microprocessor in 45 nm CMOS without detailed knowledge of its internal architecture to demonstrate the techniques automated capability. The flip-flop based design was converted to two-phase latch timing using commercial retiming tools; Bubble Razor was then inserted using automatic scripts. This system marks the first published implementation of a Razor-style scheme on a complete, commercial processor. It provides an energy efficiency improvement of 60% or a throughput gain of up to 100% compared to operating with worst case timing margins.

Bubble Razor: An architecture-independent approach to timing-error detection and correction

Several methods that eliminate timing margins by detecting and correcting transient delay errors have been proposed. These Razor-style systems replace critical flip-flops with ones that detect late arriving signals, and use architectural replay to correct errors. However, none of these methods have been applied to a complete commercial processor due to their architectural invasiveness. In addition, these Razor techniques introduce significant hold time constraints that are difficult to meet given worsening timing variability. To address these two issues we propose Bubble Razor (B-Razor), which uses a novel error-detection technique based on two-phase latch timing and a local replay mechanism that can be inserted automatically in any design. The error detec tion technique breaks the dependency between minimum delay and speculation window, restoring hold-time constraints to conventional values and allowing timing speculation of up to 100% of nominal delay. The large timing specula tion makes Bubble Razor especially applicable to low-voltage designs where tim ing variation grows exponentially.

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores

Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (~200mV above Vth) to optimally balance power and performance [1]. In Centip3De, we operate cores at 650mV, as opposed to the wear-out limited supply voltage of 1.5V. This improves measured energy efficiency by 5.1×. The dramatically lower power consumption of NTC makes it an attractive match for 3D design, which has limited power dissipation capabilities, but also has improved innate power and performance compared to 2D design.

A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells

An 8.75 mm3 microsystem targeting temperature sensing achieves zero-net-energy operation using energy harvesting and ultra-low-power circuit techniques. A 200 nW sensor measures temperature with -1.6 °C/+3 °C accuracy at a rate of 10 samples/sec. A 28 pJ/cycle, 0.4 V, 72 kHz ARM Cortex-M3 microcontroller processes temperature data using a 3.3 fW leakage per bit SRAM. Two 1 mm2 solar cells and a thin-film Li battery power the microsystem through an integrated power management unit. The complete microsystem consumes 7.7 μ W when active and enters a 550 pW data-retentive standby mode between temperature measurements. The microsystem can process temperature data hourly for 5 years using only the initial energy stored in the battery. This lifetime is extended indefinitely using energy harvesting to recharge the battery, enabling energy-autonomous operation.

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter

Advanced CMOS technologies have become highly susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses relies on canary circuits [1] or sensors [2], which are simple to implement but cannot account for local variations. A more recent approach, called Razor, uses delay speculation coupled with error detection and correction to remove all margins but also imposes significant design complexity [3]. In this paper, we present a minimally-invasive in situ delay slack monitor that directly measures the timing margins on critical timing signals, allowing margins due to both global and local PVT variations to be removed.

A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

A low leakage memory is an indispensable part of any sensor application that spends significant time in standby (sleep) mode. Although using high Vth (HVT) devices is the most straightforward way to reduce leakage, it also limits operation speed during active mode. In this paper, a low leakage 10T SRAM cell, which compensates for operation speed using a readily available secondary supply, is proposed in a 0.18µm CMOS process. It achieves the lowest-to-date leakage power consumption and achieves robust operation at low voltage without sacrificing operation speed. The 10T SRAM has a bitcell area of 17.48µm2 and is measured to consume 1.85fW per bit at 0.35V.

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS

We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is >; 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

Centip3De: A 64-Core, 3D Stacked Near-Threshold System

Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W.

A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold

A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.