Matthew T Herrick

Development of an i-line attenuated phase shift process for dual inlay interconnect lithography

The transition from aluminum/oxide to copper/low-k dielectric interconnect technology involves a variety of fundamental changes in the back-end manufacturing process. The most attractive patterning strategy involves the use of a so-called dual inlay approach, which offers lower fabrication costs by the elimination of one inter-level dielectric (ILD) deposition and polish sequence per metal layer. In this paper, the lithographic challenges for dual inlay, including thin-film interference effect, resist bulk effect, and optical proximity effects are reviewed. The use of attenuated phase shift (aPSM) reticles for patterning vias and trenches was investigated, and shown to provide adequate process margin by optimizing the photoresist and exposure tool parameters. Our results indicate that using appropriately sized attenuated phase shift technique increases the photospeed considerably and simultaneously improves the common process window with sufficient sidelobe suppression margin. The cost of ownership tradeoffs between an attenuated PSM I-Line process and a DUV binary process are discussed.