Cindy Goldberg

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.

Integration of SiCN as a low /spl kappa/ etch stop and Cu passivation in a high performance Cu/low /spl kappa/ interconnect

This paper describes the integration of a silicon carbon nitride (SiCN) copper passivation and etch stop layer into a Cu low k dielectric interconnect technology. The incorporation of SiCN improves interconnect performance by virtue of its lower dielectric constant as compared to silicon nitride, and through changes to the process integration made possible by the improved etch selectivity and good copper interface properties.

Integration challenges of 0.1 /spl mu/m CMOS Cu/low-k interconnects

The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 /spl mu/m CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.

Interconnect mechanical reliability with low /spl kappa/ dielectric as final ILD

The use of low /spl kappa/ materials as the final intralayer dielectric (ILD) layer can impact the integrity of edge seals, blown fuses, and even the interface integrity at lower levels. Furthermore, the influence of the final ILD on lower levels depends on the total number of metal levels in the product. This paper addresses the role of final ILD in both environmental and package reliability, and the use of predictive modeling of mechanical reliability.