Matthias Dyer

A systematic approach to the design of distributed wearable systems

Wearable computing has recently gained much popularity as an ambitious vision for future personalized mobile systems. Its aim is intelligent, environment aware systems unobtrusively embedded into the mobile environments of their users. With the combination of complex processing requirements, the necessity of placing sensors and input/output modules at different locations on the users body, and stringent limits on size, weight, and battery capacity, the design of such systems is an inherently challenging problem. We demonstrate how systematic design and quantitative analysis can be applied to wearable architectures. We first present a model that allows various factors influencing the design of a wearable system to be incorporated into formal cost metrics. In particular, we show how to consistently incorporate specific wearable factors such as device placement requirements, ergonomics, and dynamic workload profiles into the model. We then discuss how efficient estimation algorithms can be extended and applied to the evaluation of different architectures with respect to our cost metrics. Finally, we discuss quantitative results from a proof-of-concept case study showing the trade offs between different architectures for a given wearable scenario. Summarized, we demonstrate how the description and the design of wearable systems can be put on a systematic, formal basis allowing us to treat them similar as conventional embedded systems.

Partially Reconfigurable Cores for Xilinx Virtex

Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task.In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.

Next-generation prototyping of sensor networks

Large-scale deployment of sensor networks is more and more becoming an issue to researchers and industry alike. The recently revised BTnode architecture provides two wireless radios and facilitates the interconnection of heterogeneous devices. Apart from offering interesting new opportunities in using multi-frontend devices in sensor-network research, this architecture is optimally suited for deployment-support networks as introduced in the following.

Scalable topology control for deployment-support networks

Deployment-support networks (DSNs) have been proposed as a novel tool for the development, test, deployment, and validation of wireless sensor networks. They are expected to enhance scalability and flexibility in deployment by eliminating cable connections. In this paper, we describe our implementation of a DSN, giving details on the algorithms for topology control and maintenance. We provide various measurements of DSNs spanning up to 71 BTnode rev3 devices, featuring the largest Bluetooth scatternet reported to date. We also discuss our experience gained in the development and experimentation. Our results strongly suggest that our implementation scales well to a large number of nodes.

S-XTC: A Signal-Strength Based Topology Control Algorithm for Sensor Networks

We present S-XTC, a topology control algorithm that uses the received signal strength indicator (RSSI) of the radio on wireless sensor nodes. The algorithm is based on XTC, a practical topology control algorithm that constructs a relative neighborhood graph. In contrast to the pure XTC our extensions add to the robustness and resilience against fluctuation in the RSSI values. While guaranteeing connectivity and a bounded node degree, network topologies are able to adapt to gradual changes in the network and its environment. In this paper, we discuss the shortcomings of the previous algorithm and evaluate S-XTC by analytical proofs and simulation results. Furthermore, we have successfully implemented and tested S-XTC on the BTnode platform of which we discuss a case study and performance evaluation

The power consumption of Bluetooth scatternets

Low power has become a primary concern in the field of ad‐hoc and personal area networks. As manufacturers start endowing their designs with scatternet support, Bluetooth is emerging as a key enabling technology. Although this is driving research on Bluetooth power optimization, most proposals are based on over‐simplified, fully theoretical, or old and inadequate power models. We present a real‐world power model of a Bluetooth device supporting scatternets and sniff‐mode, and validate it experimentally on a real implementation. Whilst guaranteeing a low computational complexity, the model achieves a 4% RMS error and can be a precious aid in the design and implementation of power‐critical Bluetooth applications.

Automated Wireless Sensor Network Testing

The design of distributed, wireless, and embedded system is a tedious and error-prone process. Experiences from previous real-world wireless sensor network (WSN) deployments strongly indicate that it is vital to follow a systematic design approach to satisfy all design requirements including robustness and reliability. Such a design methodology needs to include an end-to-end testing methodology. The proposed framework for WSN testing allows to apply distributed unit testing concepts in the development process. The tool flow decreases test time and allows for monitoring the correctness of the implementation throughout the development process.

Efficient execution of process networks on a reconfigurable hardware virtual machine

In this paper, we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We use the process networks model as a coordination language which is interpreted on a virtual machine run-time system. We present and discuss the results of a design space exploration, which evaluates the performance of the system architecture for different configurations.