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Featured researches published by Matthias Schoebinger.


visual communications and image processing | 1992

Hierarchical multiprocessor system for video signal processing

Joerg Wilberg; Matthias Schoebinger; Peter Pirsch

The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area X processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 micrometers CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 micrometers CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm2.


international symposium on circuits and systems | 1988

Video chip set for data rate compression by filtering and DPCM coding

Bernd Zehner; Hans Jürgen Mattausch; Fred Matthiesen; Matthias Schoebinger; Reinhard Tielert; H. Klar; K.H. Moehrmann

Low-cost transmission of digital color TV signals for ISDN needs a data reduction to reduce the required channel bandwidth. A CMOS chip set performing a data rate compression from 140 Mb/s to 34 Mb/s is presented. It consists of a digital filter of sixth order switchable to horizontal or vertical filtering, an adjustable delay line, and a DPCM codec with a two-dimensional prediction algorithm and an adaptive quantizer characteristic. A set of experimental chips has been realized to demonstrate the feasibility of compact low-cost system components and to explore the potential of advanced CMOS technologies. Fully functional first silicon in 1.5- mu m CMOS technology was obtained. The achieved performance data guarantee correct function even under worst-case conditions.<<ETX>>


Archive | 1988

Arrangement for past DPCM coding of video signals according to a 2-D or 3-D coding method

Bernd Zehner; Fred Matthiesen; Matthias Schoebinger; Ulrich Totzek


Archive | 1989

Arrangement for DPCM-coding with high data rate

Hans-Juergen Mattausch; Fred Matthiesen; Matthias Schoebinger


Archive | 1989

Arrangement for DPCM-coding of video signals

Hans Jürgen Mattausch; Fred Matthiesen; Matthias Schoebinger


design automation conference | 1994

Low Power CMOS Design Strategies

Matthias Schoebinger; Tobias G. Noll


Archive | 1994

Processor for comparing blocks of picture elements (block matching processor)

Vos Luc De; Matthias Schoebinger


Archive | 1994

Prozessor zum vergleich von bildpunkt-blöcken (block-matching-prozessor) Processor for comparison of pixel-blocks (block-matching processor)

Vos Luc De; Matthias Schoebinger


Archive | 1994

Processor for comparison of pixel blocks (block matching processor)

Vos Luc De; Matthias Schoebinger


Journal of Pain and Symptom Management | 1988

A Single-Chip Adaptive DPCM Intrafield Video Codec

Matthias Schoebinger; Bernd Zehner; Fred Matthiesen; Ulrich Totzek; Jutta Haertl; Udo Reimann

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