Fred Matthiesen

A memory-based high-speed digital delay line with a large adjustable length

The digital delay line concept is based on a dynamic three-transistor cell memory, with pointer access and offers high operating frequency, large maximum length, and low power dissipation. The adjustable delay requires only a small overhead for control logic. An experimental chip with 60 K transistors, which utilizes this concept, has been built in a 1.5- mu m CMOS technology. The adjustable delay ranges from 1 to 4096 clock cycles for a 4-bit-wide data word. Correct operation of the chip has been verified for clock frequencies in the range of 3 kHz to 30 MHz. Therefore the circuit is suitable for audio as well as video applications. >

A CMOS VLSI chip for filtering of TV pictures in two dimensions

Low-cost digital transmission of color TV signals over the channels of a future broad-band network (Integrated Services Digital Network, or ISDN) requires data reduction by digital low-pass filters. Low-pass filtering of a TV picture amounts to process pixels which are adjacent in either the horizontal or vertical direction. For this purpose, the pixels must be stored in a delay unit. A VLSI chip with a delay unit is reported that is based on a resettable first-in-first-out (FIFO) memory and a pipelined arithmetic unit. The FIFO concept starts from a three-transistor cell array which is accessed by a pointer and customized to a FIFO memory by suitable second-layer metal wiring. Rather than cascade registers, the FIFO memory can be adapted to different standards by the reset signal for the pointer. The approach results in a regular compact design (80-kbit transistors, 31 mm/SUP 2/). An experimental chip fabricated with 1.5-/spl mu/m CMOS technology operates up to 22 MHz (typical values). A data stream of 22/spl times/32 Mb/s is exchanged between the memory and the arithmetic basic unit.

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 mu m CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz. >

Video chip set for data rate compression by filtering and DPCM coding

Low-cost transmission of digital color TV signals for ISDN needs a data reduction to reduce the required channel bandwidth. A CMOS chip set performing a data rate compression from 140 Mb/s to 34 Mb/s is presented. It consists of a digital filter of sixth order switchable to horizontal or vertical filtering, an adjustable delay line, and a DPCM codec with a two-dimensional prediction algorithm and an adaptive quantizer characteristic. A set of experimental chips has been realized to demonstrate the feasibility of compact low-cost system components and to explore the potential of advanced CMOS technologies. Fully functional first silicon in 1.5- mu m CMOS technology was obtained. The achieved performance data guarantee correct function even under worst-case conditions.<<ETX>>