Matthias Wesseling

WSI architecture of a neurocomputer module

Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm/sup 2/ soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons.<<ETX>>

Systolic Synthesis of Neural Networks

The analysis of today’s neural paradigmas brings to light a set of elementary compute-intensive algorithmic strings which are shared by all neural models and, thus, make sense to be implemented in hardware. 2D arrays composed of a systolic neural signal processor module that integrates these elementary strings as hard-wired functional blocks present a favourable solution to the architectural problem of mapping neural parallelity and adaptivity into silicon. The proposed neurocomputer concept is sizeable to the applicational domain in terms of processing power, memory and flexibility, and is designed for throughput rates which enable the user to access real-world applications in reasonable time. Throughput rates at the chip site of the order of 5·102 MC/sec (1 Connection= 16 bit) are to be expected with 0.8µm CMOS technology. By systolic extension to the board level 105 MC/sec should be attainable.

Application description concept with system level hardware abstraction

Within a recent project at Siemens Communication, we developed a new programming concept called virtual radio engine (VRE), with the goal to provide an efficient development environment for software defined radio (SDR) applications. VRE separates the development process into two steps: first, the application is described in a hardware-independent way using the VRE programming language, and then the implementation is done (to a great part) automatically by the VRE code generator system. As the hardware underlying SDR requires parallel architectures of different kinds to achieve the required high performance within a low power consumption budget, hardware-specific requirements are excluded from the VRE program. Instead, a separate hardware description file supplements the program. Therefore, the application can be described without any prior knowledge of the target hardware, and the same program can be implemented on different parallel hardware platforms. This paper concentrates on the VRE programming language and the graphic representation of VRE programs using Simulink. Special emphasis is given to the representation of different types of control flow.

Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area

The overhead of defect-tolerant circuits, such as test logic, control logic and additional datalines, increases immensely with the amount of redundancy provided by the configuration methods so far known for 2-dimensional arrays of modules. Thus, only arrays of modules with relatively little redundancy are practical. This paper suggests a method of configuration for which the overhead of each module stays small, even with rising redundancy. Furthermore, the modules and wiring have separate redundancy and they are configurated separately. Because of these two aspects a higher yield per area can be reached, especially for great word width, large modules or high defect density.

A new programming environment for software defined radio applications

The mobile communication market is confronted with an increasing number of communication standards and a corresponding complexity of the mobile terminal applications. To cope with this complexity, the Software Defined Radio (SDR) approach gains more and more attractiveness. Hardware platforms for SDR must meet the conflicting goals of flexibility, that is support for different protocols, and low power consumption. Therefore, upcoming platforms deploy parallelism, which complicates software development and requires specific knowledge about the hardware architecture. To simplify the development process, we suggest to separate the application development process into two steps, such that developers only need experience in either the software or the hardware area. In the first step, the application is specified in a hardware-independent way, and in the second step, the hardware-specific implementation is done by application-independent tools. We developed a new programming environment called Virtual Radio Engine (VRE) that supports this approach. This paper describes the VRE tool chain. Copyright

Treating weights as dynamical variables-a new approach to neurodynamics

The recall and learning dynamics of artificial neural networks are described by means of a partial differential equation (PDE) that may incorporate weights either as parameters or variables. For the case in which weights are interpreted as variables, a new type of neurodynamics is discovered when weights have to obey second-order differential equations called learning laws. Experiments on the association of time-varying patterns indicates the superiority of the learning law over the known types of learning rules. It is also shown that a single first-order Hamilton-Jacobi parametric PDE suffices to derive the various neurodynamical paradigms used currently.<<ETX>>