Karl Goser

Threshold logic circuit design of parallel adders using resonant tunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed.

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes

The manufacturability of logic circuits based on quantum tunnelling devices, namely double-barrier resonant tunnelling diodes (RTD), is studied in detail. The homogeneity and reproducibility of III/V mesa technology-based devices is experimentally evaluated and interpreted using multiple I-V characteristic simulations. The experimental sensitivity of the RTD I-V parameters on well and barrier thickness is compared with multiple I-V simulations. With shrinking minimum feature size the fluctuations in the peak current can be directly attributed to an RTD area variation caused by the increasing impact of lithography and etching on lateral dimensions. These results prove that the III/V technology fulfils the requirements for a large scale integration of RTD devices. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is presented. Detailed SPICE simulations using the experimental data show that clock and supply voltage fluctuations are tolerated up to ± 0.1 V at a supply voltage of 0.7 V. Very strong local peak voltage variations of 15 per cent in opposite directions would be necessary to have a critical impact on to the circuit functionality. Smaller deviations only affect the timing without degrading the reliability of the circuit. Consequently, the design of a stable power supply and clocking scheme is more important for the overall circuit performance than the small relative deviations of the RTD peak voltage.

Nanoelectronics and Nanosystems

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What kind of hardware is necessary for a fuzzy rule based system

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Novel MOBILE gates with low-power, relaxed parameter sensitivity, and increased driving capability

Special hardware for a fast evaluation of fuzzy rule based systems (FRBSs) are available, but in most applications only standard hardware or specific non-fuzzy ASICs are used. In this paper we discuss some of the reasons of this gap and give hints for a fast realization of FRBSs, especially on digital standard processors. For the realization, a fast algorithm with an optimized calculation of the antecedent of the fuzzy rules is introduced which minimises the number of operations. This is possible because the FRBS is a universal approximator. Furthermore, some implementation possibilities are discussed depending on their complexity.<<ETX>>

Circuit and application aspects of tunnelling devices in a MOBILE configuration

Negative-differential resistance devices, i.e. Resonant Tunneling Diodes (RTD) have recently enabled a substantial improvement in low-power memories and high-speed logic gates. For logic circuits two series connected RTDs are monolithically integrated with parallel HFET input branches building the monostable-bistable transition logic element (MOBILE). In this paper we report on drastic improvements of the MOBILE concept addressing the major restrictions: trade-off between output driving capability, number of inputs and additional current for the parallel input branches, critical design criteria for two independent technologies: HFET (threshold voltage, lateral current density) and RTD (device area, vertical current density).

Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors

In this paper, circuit and application aspects of different monostable–bistable transition logic elements (MOBILEs) are analysed. By taking advantage of the multi-state behaviour of resonant tunnelling devices (RTD) the logic depth and the circuit complexity per logic function is reduced at the gate level. Both, simulation and measurement results prove correct circuit operation in the gigahertz regime and I–O compatibiliy of the logic voltage levels. The scaling laws of the different MOBILEs are compared to each other in terms of speed and power dissipation. Detailed SPICE simulations based on experimental data precisely analyse the impact of fluctuations on the circuit functionality and performance. This study demonstrates that RTD-based MOBILEs are ready for use in digital circuitry such as linear threshold gates which offer a highly reduced circuit complexity. Copyright

Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays

A number of applications of self organizing feature maps require a powerful hardware. The algorithm of SOFMs contains multiplications, which need a large chip area for fast implementation in hardware. In this paper a resticted class of self organizing feature maps is investigated. Hardware aspects are the fundamental ideas for the restictions, so that the necessary chip area for each processor element in the map can be much smaller then before and more elements per chip can work in parallel. Binary input vectors, Manhatten Distance and a special treatment of the adaptation factor allow an efficient implementation. A hardware design using this algorithm is presented. VHDL simulations show a performance of 25600 MCPS (Million Connections Per Second) during the recall phase and 1500 MCUPS (Million Connections Updates Per Second) during the learning phase for a 50 by 50 map. A first standard cell layout containing 16 processor elements and full custom designs for the most important parts are presented.

InP-based monolithically integrated RTD/HBT MOBILE for logic circuits

This paper describes an optimized fuzzy controller (FC) architecture and its realization with field programmable gate arrays (FP-GAs). In consideration of data dependencies and minor user restrictions within the definition of fuzzy rules (FRs), it is possible to develop a high speed FPGA architecture. A prototype of the FC operates at 5MHz and needs 50μs operation time (8 bit resolution) independent of the number of inputs/outputs with 256 fuzzy rules. A pipeline architecture is used to achieve a high processing speed.

Implementation of a biologically inspired neuron-model in FPGA

A pseudo dynamic logic family is developed on InP-substrates based on the MOBILE concept. The conventional HFET as input terminal is replaced by a monolithically integrated series combination of a HBT and a RTD forming a RTBT. This combination enables a logic function defined by the RTD area only. The HBT provides a robust enhancement type operation, although for full level compatibility a buffer inverter is still necessary. A novel distributed clocking scheme is developed. The feasibility of this logic concept is experimentally verified and an OR gate is discussed in detail.