Maurice Sebastian
Braunschweig University of Technology
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Publication
Featured researches published by Maurice Sebastian.
ACM Transactions in Embedded Computing Systems | 2014
Philip Axer; Rolf Ernst; Heiko Falk; Alain Girault; Daniel Grund; Nan Guan; Bengt Jonsson; Peter Marwedel; Jan Reineke; Christine Rochange; Maurice Sebastian; Reinhard von Hanxleden; Reinhard Wilhelm; Wang Yi
A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.
international conference on hardware/software codesign and system synthesis | 2011
Philip Axer; Maurice Sebastian; Rolf Ernst
Methods such as rollback and modular redundancy are efficient to correct transient errors. In hard real-time systems, however, correction has a strong impact on response times, also on tasks that were not directly affected by errors. Due to deadline misses, these tasks eventually fail to provide correct service. In this paper we present a reliability analysis for periodic task sets and static priorities that includes realistic detection and roll-back scenarios and covers a hyperperiod instead of just a critical instant and therefore leads to much higher accuracy than previous approaches. The approach is compared with Monte-Carlo simulation to demonstrate the accuracy and with previous approaches covering critical instants to evaluate the improvements.
pacific rim international symposium on dependable computing | 2009
Maurice Sebastian; Rolf Ernst
Due to continuous technology downscaling modern embedded real-time systems become more and more susceptible to the occurrence of errors. The usage of appropriate countermeasures is necessary to prevent a system failure. In this paper we present a new reliability estimation technique for such systems. As a key novelty a formal analysis method will be introduced that approximates the probability of failure of a priority driven bus during a period of time, enabling fast and accurate reliability calculation. It removes the major drawbacks of existing approaches, e.g. random-based Monte-Carlo simulation that requires long runtimes. However Monte-Carlo simulation serves as reference method to demonstrate the accuracy of our approach by comparing analysis and simulation results. Finally we consider the design of mixed-criticality systems which combine different safety requirements on a single component.
design, automation, and test in europe | 2012
Philip Axer; Maurice Sebastian; Rolf Ernst
The controller area network (CAN) is widely used in industrial and the automotive domain and in this context often for hard real-time applications. Formal methods guide the designer to give worst-case guarantees on timing. However, due to bit errors on the communication channel response times can be delayed due to retransmissions. Some methods exist to cover these effects, but are limited e.g. (support only periodic real-time traffic). In this paper we generalize existing methods to support arbitrary deadlines, and derive a probabilistic response time bound which is especially useful with the emergence of the new automotive safety standard ISO 26262.
emerging technologies and factory automation | 2008
Maurice Sebastian; Rolf Ernst
Due to continuous technology downscaling modern MPSoCs become more and more susceptible to the occurrence of internal errors in computational cores as well as in the on-chip-communication infrastructure. The usage of appropriate techniques is necessary to counteract these errors and thus preventing them from originating a system failure. In this paper we will explore the impact of fault tolerance mechanisms for on-chip communication components in real-time systems. Therefore we will introduce a behavioural model of on-chip communication including a simple simulation framework that can easily be adapted to existing system-on-chip bus architectures. Based on that model several simulations will be performed to determine the reliability of an exemplary on-chip-bus. Our experimental results show that design decisions concerning fault tolerance strongly rely on platform and application characteristics like transmission speed or communication amount.
pacific rim international symposium on dependable computing | 2011
Maurice Sebastian; Philip Axer; Rolf Ernst
In the near future embedded systems will be faced with the phenomena of increasing error rates, caused by a variety of error sources that have to be considered during the design process. In this paper we propose a method to derive the reliability of a real-time capable CAN bus system with errors. Individual errors on the CAN bus might be correlated in arbitrary way, the proposed algorithm will cover this. It is based on a previous work on reliability analysis that has been restricted to uncorrelated bit errors. To extend this approach we first introduce a suitable error model to describe arbitrary correlations between bit errors. As a key novelty we present an extended analysis procedure that takes this error model into account. This new approach will be utilized to determine the effects of burst errors and to demonstrate the necessity of appropriate error models for reliability analysis.
Ipsj Transactions on System Lsi Design Methodology | 2011
Philip Axer; Jonas Diemer; Mircea Negrean; Maurice Sebastian; Simon Schliecker; Rolf Ernst
Multi-Processor Systems-on-Chips (MPSoCs) emerge as the predominant platform in embedded real-time applications. A large variety of ubiquitous services should be implemented by embedded systems in a cost- and power-efficient way, yet providing a maximum degree of performance, usability and dependability. By using a scalable Network-on-Chip (NoC) architecture which replaces the traditional point-to-point and bus connections in conjunction with performant IP cores it is possible to use the available performance to consolidate functionality on a single MPSoC platform. But especially when uncritical best-effort applications (e.g., entertainment) and critical applications (e.g., pedestrian detection, electronic stability control) are combined on the same architecture (mixed-criticality), validation faces new challenges. Due to complex resource sharing in MPSoCs the timing behavior becomes more complex and requires new analysis methods. Additionally, applications that may exhibit multiple behaviors corresponding to different operating modes (e.g., initialization mode, fault-recovery mode) need to be also considered in the design of mixed-critical MPSoCs. In this paper, challenges in the design of mixed-critical systems are discussed and formal analysis solutions which consider shared resources, NoC communication, multi-mode applications and their reliabilities are proposed.
SAE 2013 World Congress & Exhibition | 2013
Christoph Ficek; Maurice Sebastian; Nico Feiertag; Kai Richter; Marek Jersak; Karsten Schmidt
SAE 2011 World Congress & Exhibition | 2011
Maurice Sebastian; Philip Axer; Rolf Ernst; Nico Feiertag; Marek Jersak
WCX™ 17: SAE World Congress ExperienceSAE International | 2017
Andre Kohn; Karsten Schmidt; Jochen Decker; Maurice Sebastian; Alexander Züpke; Andreas Herkersdorf