Simon Schliecker

Scheduling analysis of real-time systems with precise modeling of cache related preemption delay

Accurate timing analysis is key to efficient embedded system synthesis and integration. Caches are needed to increase the processor performance but they are hard to use because of their complex behaviour especially in preemptive scheduling. Current approaches use simplified assumptions or propose exponentially complex scheduling analysis algorithms to bound the cache related preemption delay at a context switch. We present a conservative polynomial algorithm that extends real-time scheduling analysis to consider cache effects due to the preempted and the preempting task for the preemption delay. Dataflow analysis on task level is combined with real-time scheduling analysis to determine the response time including cache related preemption delay for each task accurately. The experiments show significant improvement in analysis precision over previous polynomial approaches for typical embedded benchmarks.

Bounding the shared resource load for the performance analysis of multiprocessor systems

Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new inter-core timing dependencies, resulting from the common use of the now shared resources. In order to conservatively bound the delay due to the shared resource accesses, upper bounds on the potential amount of conflicting requests from other processors are required. This paper proposes a method that captures the request distances of multiple shared resource accesses by single tasks and also by multiple tasks that are dynamically scheduled on the same processor. Unlike previous work, we acknowledge the fact that on a single processor, tasks will not actually execute in parallel, but in alternation. This consideration leads to a more accurate load model. In a final step, the approach is extended to allow addressing also dynamic cache misses that do not occur at predefined times but surface dynamically during the execution of the tasks.

Influence of different system abstractions on the performance analysis of distributed real-time systems

System level performance analysis plays a fundamental role in the design process of real-time embedded systems. Several different approaches have been presented so far to address the problem of accurate performance analysis of distributed embedded systems in early design stages. The existing formal analysis methods are based on essentially different concepts of abstraction. However, the influence of these different models on the accuracy of the system analysis is widely unknown, as a direct comparison of performance analysis methods has not been considered so far. We define a set of benchmarks aimed at the evaluation of performance analysis techniques for distributed systems. We apply different analysis methods to the benchmarks and compare the results obtained in terms of accuracy and analysis times, highlighting the specific effects of the various abstractions. We also point out several pitfalls for the analysis accuracy of single approaches and investigate the reasons for pessimistic performance predictions.

Providing accurate event models for the analysis of heterogeneous multiprocessor systems

This paper proposes a new method for deriving quantitative event information for compositional multiprocessor performance analysis. This procedure brakes down the complexity into the analysis of individual components (tasks mapped to resources) and the propagation of the timing information with the help of event models. This paper improves previous methods to derive event models in a multiprocessor system by providing tighter bounds and allowing arbitrarily shaped event models. The procedure is based on a a simple yet expressive resource model called the multiple event busy time which can be derived on the basis of classical scheduling theory -- it can therefore be provided for a large domain of scheduling policies. Our experiments show that overestimation by previous methods can be reduced significantly.

System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures

Software timing aspects have only recently received broad attention in the automotive industry. New design trends and the ongoing work in the AUTOSAR (Automotive Open System Architecture) partnership have significantly increased the industrys awareness to these issues. Now, timing is recognized as a major challenge and has been put explicitly on the agenda of AUTOSAR and other industry-driven research projects. The goals include complementing the existing standard by a timing view and adding methodological steps, if necessary. Clearly, establishing such timing models requires knowing well the implications of modern architectures and topologies. In this paper, we survey existing performance analysis approaches from real-time systems research and compare them to the established layered software architectures of automotive system design. We highlight key challenges for the application of performance analysis in this domain and identify structural as well as behavioral ldquomodeling gapsrdquo. While structural gaps can be overcome by model transformations, behavioral gaps require real extensions to known analyses. We discuss two such extensions in detail, namely, the use of hierarchical event models and the specialties of timing analysis for multicore platforms. This paper concludes with an overview over qualitative comparisons of analysis techniques, both technically and concerning their industrial applicability.

Response Time Analysis on Multicore ECUs With Shared Resources

As multiprocessor systems are increasingly used in automotive real-time environments, scheduling and synchronization analysis of these platforms receive growing attention. Upcoming multicore ECUs allow the integration of previously separated functionality for body electronics or sensor fusion onto a single unit, and allow the parallelization of complex computations over multiple cores. The application of multiple CPUs turns an ECU into a highly integrated ldquonetworked systemrdquo microcosm, in which complex interdependencies can be observed due to the use of shared resources even in partitioned scheduling. To deliver predictable performance, resource arbitration protocols are required and have been proposed in literature. This paper presents an novel analytical approach to provide the worst-case response time for real-time tasks in multiprocessor systems with shared resources. The method supports realistic, event- or time-driven task activation schemes and allows to calculate tight bounds on the estimated system performance.

Reliable performance analysis of a multicore multithreaded system-on-chip

Formal performance analysis is now regularly applied in the design of distributed embedded systems such as automotive electronics, where it greatly contributes to an improved predictability and platform robustness of complex networked systems. Even though it might be highly beneficial also in MpSoC design, formal performance analysis could not easily be applied so far, because the classical task communication model does not cover processor-memory traffic, which is an integral part of MpSoC timing. Introducing memory accesses as individual transactions under the classical model has shown to be inefficient, and previous approaches work well only under strict orthogonalization of different traffic streams. Recent research has presented extensions of the classical task model and a corresponding analysis that covers performance implications of shared memory traffic. In this paper we present a multithreaded multiprocessors platform and multimedia application. We conduct performance analysis using the new analysis options and specifically benchmark the quality of the available approach. Our experiments show that corner case coverage can now be supplied with a very high accuracy, allowing to quickly investigate architectural alternatives.

Real-time performance analysis of multiprocessor systems with shared memory

Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new intercore timing dependencies resulting from the common use of the now shared resources. This feedback of system timing on local timing makes traditional performance analysis approaches inappropriate. This article presents a general methodology to model the shared resource traffic and consider its effect on the local task execution. The aggregate busy time captures the timing of multiple accesses to a shared memory far better than the traditional models that focus on the timing of individual events. An iterative approach is proposed to tackle the analysis dependencies that exist in systems with event-driven task activation and dynamic resource arbitration.

Integrated analysis of communicating tasks in MPSoCs

Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication networks, basic operations of every embedded application pose a challenge for precise system analysis. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside a component, abstracting system level influences by over estimations. In this paper, we identify feedbacks of the system behavior that directly or indirectly impact local execution. To tackle these complex interactions we present a novel technique to integrate an extended component level scheduling analysis with refined system level approaches. Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures - which could not be addressed on a single level alone. On the component level, we investigate two scheduling behaviors more closely, namely stalling during external requests, and allowing context-switches to other tasks that are ready. For both, we present a precise response time analysis. Finally, we compare the scheduling techniques with respect to real-time requirements.

A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems

This paper proposes a method for the derivation of end-to-end delays of applications that involve processing on multiple components in a heterogeneous multiprocessor system. The rocedure precisely captures the pipelined and parallel processing of multiple events along an application path by accurately capturing the resource timing and avoiding the pay-bursts-only-once problem. Both time-triggered and event-triggered task activation schemes with arbitrary event patterns are supported. In contrast to previous work, complex application topologies are allowed: The approach considers path forking and merging, as well as functional cycles and non-functional cyclic dependencies. The basis for the proposed method is an iterative compositional performance analysis, that allows computing event models in such systems. Based on the event models and local performance abstractions we propose a recursive approach to the derivation of the worst-case latency.