Mazhareddin Taghivand

Supporting and Enabling Circuits for Antenna Arrays in Wireless Communications

Antenna arrays have been demonstrated as a very promising technique for high-speed wireless networks, and are anticipated to be indispensable components in future wireless communication systems. This review paper presents an overview of the circuit techniques on combining signals from different receive array elements as well as splitting signals to different transmit array elements with emphasis on silicon-based solutions. It also reviews circuit techniques to control the phase and the amplitude of signals from/to each array element such that signals from those array elements can be combined and split in a desired manner for achieving high data rate communications as well as interference management.

On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (fο) and second harmonic (2fο) and then mixes them together to obtain the desired mm-wave third-harmonic (3fο). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3fο, the proposed SMV architecture achieves about 2× higher FTR and a better PN performance. A 52.8-62.5 GHz SMV prototype is designed and implemented in a 0.13 μm CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6 dBc/Hz at 1 MHz offset-resulting in an FTR-inclusive figure-of-merit (FoMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply.

A compact 24–54 GHz CMOS band-pass distributed amplifier for high fractional bandwidth signal amplification

This paper describes a compact 24-54 GHz two-stage band-pass distributed amplifier (BPDA) utilizing dual mirror-symmetric Norton transformations to reduce inductor component values allowing an area-efficient layout. The BPDA, implemented in a 40nm CMOS process, occupies an active area of 0.15mm2, has a 77% fractional-bandwidth, an overall gain of 7dB, a minimum in-band IIP3 of 11dBm, inband noise-figure less than 6.2dB while consuming 34mA from a 1V supply.

A Millimeter-Wave Digital Link for Wireless MRI

A millimeter (mm) wave radio is presented in this work to support wireless MRI data transmission. High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI. The proposed system uses a custom designed integrated chip (IC) mm-wave radio with 60 GHz as radio frequency carrier. In this work, we assess performance in a 1.5 T MRI field, with the addition of optical links between the console room and magnet. The system uses ON-OFF keying (OOK) modulation for data transmission and supports data rates from 200 Mb/s to 2.5 Gb/s for distances up-to 65 cm. The presence of highly directional, linearly polarized, on-chip dipole antennas on the mm-wave radio along with the time division multiplexing (TDM) circuitry allows multiple wireless links to be created simultaneously with minimal inter-channel interference. This leads to a highly scalable solution for wireless MRI.

A 55–70GHz two-stage tunable polyphase filter with feedback control for quadrature generation with <2° and <0.32dB phase/amplitude imbalance in 28nm CMOS process

An integrated two-stage polyphase filters (PPFs) with feedback control is proposed for local oscillator (LO) quadrature generation at millimeter-wave band frequencies. The PPFs second stage utilizes triode-region NMOS transistors to implement variable resistors which are accurately controlled to minimize any IQ mismatch. A prototype quadrature signal generator for use in a homodyne 60GHz receiver is integrated in 28nm LP CMOS process. A worst-case measured phase and amplitude imbalance of 2o and 0.32dB across a frequency range of 55-70GHz is reported. The core IQ generator size is 20μ m × 40μ m while consuming 81 μW, which includes 9μW for the feedback control loop and 40A from 1.8V supply for the opamp. The input impedance is simulated to be 150Q in parallel with 18fF.

A Compact 77% Fractional Bandwidth CMOS Band-Pass Distributed Amplifier With Mirror-Symmetric Norton Transforms

This paper presents the design of a high fractional-bandwidth millimeter-wave band-pass distributed amplifier (BPDA) implemented in a 40 nm (LP) CMOS process. A high-order load impedance with multiple resonant elements is often used to realize wideband amplifiers. However, these implementations require the use of numerous inductors which occupy a prohibitively large amount of silicon area. A mirror-symmetric Norton transformation technique which reduces inductor component values for a wideband amplifier, allowing an area-efficient layout, is described in this paper. The BPDA consumes 34 mW while providing a power-gain of 7 dB from 24-to-54 GHz with less than 2 dB in-band gain-variation. The BPDA has a measured 77% fractional bandwidth, a +11 dBm in-band IIP3, and an in-band noise-figure less than 6.2 dB, while occupying an area of 0.15 mm2.

21.5 A 3.24-to-8.45GHz low-phase-noise mode-switching oscillator

VCO design for cellular applications to achieve universal coverage for a wide range of frequencies (400MHz to 3700MHz) in different standards and meeting stringent out-of-band and in-band phase-noise (PN) requirements is a challenging task. The simplest method to generate I and Q signals in the LO is to use a frequency divide-by-2 which requires the VCO frequency to be an even multiple of fLO. This method is area efficient and superior for coexistence as it does not generate jammers in other bands. The technique in this work expands the VCO frequency range to ensure 2xfLO for all cellular bands, notably 3700MHz, with sufficient margin, and meets the most stringent PN specification for a SAW-less GSM transceiver.

An RF-powered 58Mbps-TX 2.5Mbps-RX full-duplex transceiver for neural microimplants

A wirelessly-powered, high-data-rate transceiver for neuro-modulation applications is presented. The transceiver achieves 58Mbps in TX, and 2.5Mbps in RX. It enables bidirectional full-duplex communication using an external duplexer. The TX operates at 1.74GHz and consumes 93μW, while the RX operates at 1.86GHz and consumes 7.2μW. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2. The overall system size including the duplexer is 3.2mm2.

An energy harvested ultra-low power transceiver for Internet of Medical Things

We present an energy harvested ultra-low power transceiver for medical applications. The proposed design is RF-powered and enables bidirectional full-duplex communication using time-division duplexing (TDD) at 1.85GHz. The transceiver achieves a data rate of 7.2Mbps in TX, and 1.8Mbps in RX. The TX consumes 54μW, while the RX consumes 9.4μW of power. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2.

An Energy Harvesting 2

A fully integrated 2 ×2 CMOS transceiver at 60 GHz with energy harvesting capability in the transmitter mode and on-chip dipole antennas is demonstrated. The radio supports on-off-keying (OOK) modulation and a programmable data rate of 38 to 2450 Mb/s at a BER of less than 5 ×10 -4. The power consumption of the transmitter scales with data rate from 100 μW to 6.3 mW at 5 cm range and from 260 μW to 11.9 mW at 10 cm range. This yields an energy efficiency of 2.6 pJ/b at 5 cm and 4.9 pJ/b at 10cm. The energy harvesting circuits operate at 2.45 GHz with an average efficiency of 33%. The harvesting antenna and its matching components are off-chip. The complete transceiver including the energy harvesting block and on-chip antennas occupies 1.62 mm 2 in 40 nm CMOS.