Yashar Rajavi

A Single-Chip CMOS Bluetooth v2.1 Radio SoC

Bluetoothcopyradios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.

A Millimeter-Wave Digital Link for Wireless MRI

A millimeter (mm) wave radio is presented in this work to support wireless MRI data transmission. High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI. The proposed system uses a custom designed integrated chip (IC) mm-wave radio with 60 GHz as radio frequency carrier. In this work, we assess performance in a 1.5 T MRI field, with the addition of optical links between the console room and magnet. The system uses ON-OFF keying (OOK) modulation for data transmission and supports data rates from 200 Mb/s to 2.5 Gb/s for distances up-to 65 cm. The presence of highly directional, linearly polarized, on-chip dipole antennas on the mm-wave radio along with the time division multiplexing (TDM) circuitry allows multiple wireless links to be created simultaneously with minimal inter-channel interference. This leads to a highly scalable solution for wireless MRI.

An RF-powered 58Mbps-TX 2.5Mbps-RX full-duplex transceiver for neural microimplants

A wirelessly-powered, high-data-rate transceiver for neuro-modulation applications is presented. The transceiver achieves 58Mbps in TX, and 2.5Mbps in RX. It enables bidirectional full-duplex communication using an external duplexer. The TX operates at 1.74GHz and consumes 93μW, while the RX operates at 1.86GHz and consumes 7.2μW. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2. The overall system size including the duplexer is 3.2mm2.

An energy harvested ultra-low power transceiver for Internet of Medical Things

We present an energy harvested ultra-low power transceiver for medical applications. The proposed design is RF-powered and enables bidirectional full-duplex communication using time-division duplexing (TDD) at 1.85GHz. The transceiver achieves a data rate of 7.2Mbps in TX, and 1.8Mbps in RX. The TX consumes 54μW, while the RX consumes 9.4μW of power. The prototype was fabricated in 40nm LP CMOS and occupies 0.8mm2.

An Energy Harvesting 2

A fully integrated 2 ×2 CMOS transceiver at 60 GHz with energy harvesting capability in the transmitter mode and on-chip dipole antennas is demonstrated. The radio supports on-off-keying (OOK) modulation and a programmable data rate of 38 to 2450 Mb/s at a BER of less than 5 ×10 -4. The power consumption of the transmitter scales with data rate from 100 μW to 6.3 mW at 5 cm range and from 260 μW to 11.9 mW at 10 cm range. This yields an energy efficiency of 2.6 pJ/b at 5 cm and 4.9 pJ/b at 10cm. The energy harvesting circuits operate at 2.45 GHz with an average efficiency of 33%. The harvesting antenna and its matching components are off-chip. The complete transceiver including the energy harvesting block and on-chip antennas occupies 1.62 mm 2 in 40 nm CMOS.

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This work presents a 980μW direct-conversion BLE receiver at a 1V supply, employing current-reuse and subthreshold techniques. The receiver has a measured noise figure of 5.2dB, integrated from 10kHz to 1MHz, that corresponds to a sensitivity of −95.8dBm. At a receiver gain of 47dB, an HP3 of −19.7dBm has been measured. The LO integrated phase noise at 2.4GHz is 0.83° with LO spot phase noise of −119.9dBc/Hz at 3MHz frequency offset. The PLL is compacted inside the VCO inductor and has LC-VCO with a tuning range of 4.55GHz to 5.15GHz. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variation. The prototype is implemented in a 40nm LP CMOS process occupying a silicon area of 0.7mm2. To the best of our knowledge, the proposed receiver achieves the highest reported figure of merit among the BLE receivers published in the literature.

2 60 GHz Transceiver With Scalable Data Rate of 38–2450 Mb/s for Near-Range Communication

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 mum CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a DeltaSigma ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit.