Md. Mazder Rahman

Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit

This paper presents a quantum gate library that consists of all possible two-qubit quantum gates which do not produce entangled states. The quantum cost of each two-qubit gate in the proposed library is one. Therefore, these gates can be used to reduce the quantum costs of reversible circuits. Experimental results show a significant reduction of quantum cost in benchmark circuits. The resulting circuits could be further optimized with existing tools, such as quantum template matching.

Properties of Quantum Templates

Identity circuits are the basis for rewriting rules in the process of optimizing reversible and quantum circuits. Rewriting rules are also known as templates. It has been shown that templates can play an important role in optimizing quantum circuits. This paper presents an in-depth study of the properties of such templates. It is shown that all optimal realizations, within certain limitations, are embedded in templates. The properties presented here, lead to a systematic method of generating all templates with a given number of lines. It is proven that, if the complete set of templates is available, template matching results in optimal circuits.

An algorithm to find quantum templates

Identity circuits can be used as templates to minimize reversible circuits. This paper describes an algorithm to find all quantum templates with 3 qubits. The algorithm is used to find all templates with up to 8 gates. The method first finds a quantum identities of 3 qubits, template matching is used to verify if the identity is a template. Experiments show the significance of templates the new to reduce the quantum costs of benchmark circuits.

Optimization of reversible circuits using reconfigured templates

This paper presents a new method to optimize the quantum costs of reversible circuits. A single quantum implementation of the Toffoli-3 gate has been used to decompose reversible circuits into quantum circuits. Reconfigured quantum templates using splitting rules are introduced. The Controlled-NOT, Controlled-V, and Controlled-V+ gates can be split into two gates --- splitting rules are derived from this fact. Quantum costs of reversible circuits are measured by the number of two-qubit operations. Therefore, the costs of reconfigured templates will be unchanged when the splitting rules are applied. Although the number of quantum gates of reconfigured templates increases, their quantum cost remains invariant. Experimental results show that significant cost reductions can be achieved with the proposed method.

An Algorithm for Quantum Template Matching

Quantum circuits are often generated by decomposing gates from networks with classical reversible gates. Only in rare cases, the results are minimal. Post-optimization methods, such as template matching, are employed to reduce the quantum costs of circuits. Quantum templates are derived from identity circuits. All minimal realizations, within certain limitations, can be embedded into templates. Due to this property, templates matching has the potential to reduce quantum costs of circuits. However, one of the difficulties in finding templates matches is due to the mobility of the gates within the circuit. Thus far, template matching procedures have employed heuristics to reduce the search space. This article presents an in-depth study of exact template matching with a set of algorithms. A graph structure with the corresponding circuits facilitates the discovery of potential sequences of templates to be matched, and how exact minimization of circuits can be accomplished. The significance of the proposed method is verified in benchmarks optimization.

Optimal Quantum Circuits of Three Qubits

This paper shows how to find the optimal quantum circuits for all 3-qubit functions with an exhaustive search. A circuit for a given function is said to be optimal, if no realization with fewer gates exists. It is important to have the optimal results for all three-input functions, since they can serve as benchmarks when evaluation heuristic optimization algorithms. The optimal results generated, are compared with optimized quantum circuits obtained from post synthesis algorithms. It is observed that the published templates do not lead to optimal results. Experimental results show, that optimal circuits can seldom be obtained with template matching. On average the optimal size of a 3-qubit circuit is 10.0, where as template matching only achieves an average of 11.9 gates. It is shown that this is due to the fact that not all templates have been discovered. The paper concludes with some directions for further research.

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits

The rapid advances of quantum technologies are opening up new challenges, of which, protecting quantum states from errors is a major one. Among quantum error correction schemes, the surface code is emerging as a natural choice with high-fidelity quantum gates reported for experimental platforms. Surface codes also necessitate the quantum gates to be formed with strict nearest neighbour coupling. State-of-the-art-reversible logic synthesis techniques for quantum circuit implementation do not ensure the logic gates to be formed in a nearest neighbor fashion, and this is handled as a post processing optimization by the insertion of swap gates. In this paper, we propose, for the first time, the inclusion of nearest neighbourhood criteria in a widely used ancilla free reversible logic synthesis method. Experimental results show that this method easily outperforms the earlier two step techniques in terms of gate count without any runtime overhead.

An extension of transformation-based reversible and quantum circuit synthesis

Transformation-based synthesis is a well established systematic approach to determine a circuit implementation from a reversible function specification. Due to the inherent bidirectionality of reversible circuits the basic method can be applied in a bidirectional manner. In the approaches to date, gates are added either to the input side or the output side of the circuit on each iteration. I n this paper, we introduce a new variation where gates may be added at both ends during a single iteration when this is advantageous to reducing the cost of the circuit. Experimental results show the advantage of the new approach over previous transformation-based synthesis methods and that the additional computation is justified by the possibility of improved circuit costs.

Trace Files for Automatic Memory Management Systems

Automated memory management is generally non-deterministic. Attempts to improve its performance require testing and simulation of basic memory management (MM) operations. Simulation of automated memory management usually involves running a virtual machine (VM) with benchmark applications. However, this process requires significant run-time. Moreover, there are few benchmarks available for programmers to test and validate their systems against. In this work, we record basic memory management operations of benchmark applications into trace files. These trace files can be used platform independently to evaluate systems off-line. Empirical results show that recording traces of memory management operations of applications into files requires large amounts of physical space. To aid developers, we also design and implement a trace synthesizer that creates basic memory operations dynamically for given specifications. The significance of trace files is shown experimentally by simulating and evaluating GC policies.

Dynamic Template Matching with Mixed-Polarity Toffoli Gates

The Toffoli gate, as originally proposed, had only positive controls. It has been shown that mixed polarity controlled Toffoli gates can be efficiently implemented. In fact, their quantum cost is the same as for positive controlled gates in most cases. Thus it is advantageous to consider circuits with mixed polarity Toffoli gates. Template matching has been successfully used to reduce the number of Toffoli gates in reversible circuits. Little work on templates with mixed polarity gates has been reported. Unfortunately, the number of potential templates increases dramatically, if mixed polarity is introduced. Here we propose a dynamic template matching algorithm that takes templates with few lines and dynamically extends the lines to find matches. Experimental results show that the proposed approach has a significant impact on reducing the total number of gates (57% in the best case) in circuits.