Medhat Moussa

The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study

In this paper, arithmetic representations for implementing multilayer perceptrons trained using the error backpropagation algorithm (MLP-BP) neural networks on field-programmable gate arrays (FPGAs) are examined in detail. Both floating-point (FLP) and fixed-point (FXP) formats are studied and the effect of precision of representation and FPGA area requirements are considered. A generic very high-speed integrated circuit hardware description language (VHDL) program was developed to help experiment with a large number of formats and designs. The results show that an MLP-BP network uses less clock cycles and consumes less real estate when compiled in an FXP format, compared with a larger and slower functioning compilation in an FLP format with similar data representation width, in bits, or a similar precision and range

An experimental approach to robotic grasping using a connectionist architecture and generic grasping functions

An experimental approach to robotic grasping is presented. This approach is based on developing a generic representation of grasping rules, which allows learning them from experiments between the object and the robot. A modular connectionist design arranged in subsumption layers is used to provide a mapping between sensory inputs and robot actions. Reinforcement feedback is used to select between different grasping rules and to reduce the number of failed experiments. This is particularly critical for applications in the personal service robot environment. Simulated experiments on a 15-object database show that the system is capable of learning grasping rules for each object in a finite number of experiments as well as generalizing from experiments on one object to grasping from another.

Combining expert neural networks using reinforcement feedback for learning primitive grasping behavior

This paper present an architecture for combining a mixture of experts. The architecture has two unique features: 1) it assumes no prior knowledge of the size or structure of the mixture and allows the number of experts to dynamically expand during training, and 2) reinforcement feedback is used to guide the combining/expansion operation. The architecture is particularly suitable for applications when there is a need to approximate a many-to-many mapping. An example of such a problem is the task of training a robot to grasp arbitrarily shaped objects. This task requires the approximation of a many-to-many mapping, since various configurations can be used to grasp an object, and several objects can share the same grasping configuration. Experiments in a simulated environment using a 28-object database showed how the algorithm dynamically combined and expanded a mixture of neural networks to achieve the learning task. The paper also presents a comparison with two other nonlearning approaches.

A hardware Memetic accelerator for VLSI circuit partitioning

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5x speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach.

A scalable pipelined architecture for real-time computation of MLP-BP neural networks

In this paper a novel architecture for implementing multi-layer perceptron (MLP) neural networks on field programmable gate arrays (FPGA) is presented. The architecture presents a new scalable design that allows variable degrees of parallelism in order to achieve the best balance between performance and FPGA resources usage. Performance is enhanced using a highly efficient pipelined design. Extensive analysis and simulations have been conducted on four standard benchmark problems. Results show that a minimum performance boost of three orders of magnitude (O^3) over software implementation is regularly achieved. We report performance of 2-67GCUPS for these simple problems, and performance reaching over 1TCUPS for larger networks and different single FPGA chips. To our knowledge, this is the highest speed reported to date for any MLP network implementation on FPGAs.

Arithmetic formats for implementing artificial neural networks on FPGAs

This paper investigates the effect of arithmetic representationformats on the implementationof artificial neural networks (ANNs) on field-programmable gate arrays (FPGAs). The focus is on examining the tradeoffs between precision and range of various formats and the required FPGA resources. Basic ANN processing elements include multiplication and addition operations. Therefore, floating-point and fixed-point multipliers/adders were implemented and tested on an FPGA, and their area requirements were compared. The results show that for multilayer perceptron neural networks, floating-point formats offer more area-efficient implementation than fixed-point formats without penalty in terms of precision or range. The results also show that the target FPGA device can have a major impact on the resourcesrequired.

Range image segmentation using local approximation of scan lines with application to CAD model acquisition

Abstract. Automatic acquisition of CAD models from existing objects requires accurate extraction of geometric and topological information from the input data. This paper presents a range image segmentation method based on local approximation of scan lines. The method employs edge models that are capable of detecting noise pixels as well as position and orientation discontinuities of varying strengths. Region-based techniques are then used to achieve a complete segmentation. Finally, a geometric representation of the scene, in the form of a surface CAD model, is produced. Experimental results on a large number of real range images acquired by different range sensors demonstrate the efficiency and robustness of the method.

Memory efficient FPGA implementation of hough transform for line and circle detection

Hough transform (HT) is a widely used algorithm in machine vision systems. In this paper, a memory efficient architecture for implementing HT on FPGAs is presented. The proposed architecture enables storing the HT space on the FPGAs memory blocks with no need for accessing external memory while processing large size images in real-time with high frame rate. It can be used for both line and circle detection. Results show very good accuracy with images processed at 30 fps frame rate and image size of 800 × 600. This compares favourably with other reported architectures in the literature.

Toward a Natural Language Interface for Transferring Grasping Skills to Robots

In this paper, we report on the findings of a human-robot interaction study that aims at developing a communication language for transferring grasping skills from a nontechnical user to a robot. Participants with different backgrounds and education levels were asked to command a five-degree-of-freedom human-scale robot arm to grasp five small everyday objects. They were allowed to use either commands from an existing command set or develop their own equivalent natural language instructions. The study revealed several important findings. First, individual participants were more inclined to use simple, familiar commands than more powerful ones. In most cases, once a set of instructions was found to accomplish the grasping task, few participants deviated from that set. In addition, we also found that the participants background does appear to play a role during the interaction process. Overall, participants with less technical backgrounds require more time and more commands on average to complete a grasping task as compared to participants with more technical backgrounds.

ON THE ARITHMETIC PRECISION FOR IMPLEMENTING BACK-PROPAGATION NETWORKS ON FPGA: A CASE STUDY

Artificial Neural Networks (ANNs) are inherently parallel architectures which represent a natural fit for custom implementation on FPGAs. One important implementation issue is to determine the numerical precision format that allows an optimum tradeoff between precision and implementation areas. Standard single or double precision floating-point representations minimize quantization errors while requiring significant hardware resources. Less precise fixed-point representation may require less hardware resources but add quantization errors that may prevent learning from taking place, especially in regression problems. This chapter examines this issue and reports on a recent experiment where we implemented a Multi-layer perceptron (MLP) on an FPGA using both fixed and floating point precision. Results show that the fixed-point MLP implementation was over 12x greater in speed, over 13x smaller in area, and achieves far greater processing density compared to the floating-point FPGA-based MLP.