Shawki Areibi

Design and optimization of multithreshold CMOS (MTCMOS) circuits

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuits routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.

The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study

In this paper, arithmetic representations for implementing multilayer perceptrons trained using the error backpropagation algorithm (MLP-BP) neural networks on field-programmable gate arrays (FPGAs) are examined in detail. Both floating-point (FLP) and fixed-point (FXP) formats are studied and the effect of precision of representation and FPGA area requirements are considered. A generic very high-speed integrated circuit hardware description language (VHDL) program was developed to help experiment with a large number of formats and designs. The results show that an MLP-BP network uses less clock cycles and consumes less real estate when compiled in an FXP format, compared with a larger and slower functioning compilation in an FLP format with similar data representation width, in bits, or a similar precision and range

Genetic algorithm for dynamic path planning

Optimization in dynamically changing environments is a hard problem. Path planning for mobile robots is a complex problem that not only guarantees a collision-free with minimum traveling distance but also requires smoothness and clearances. This paper presents a genetic algorithm approach for solving the path planning problem in stochastic mobile robot environments. The genetic algorithm planner (GAP) is based on a variable length representation, where different evolutionary operators are applied. A generic fitness function is used to combine all the objectives of the problem. In order to make the algorithm suitable for both static and dynamic environments, problem specific domain knowledge is used.

Strength pareto particle swarm optimization and hybrid ea-pso for multi-objective optimization

This paper proposes an efficient particle swarm optimization (PSO) technique that can handle multi-objective optimization problems. It is based on the strength Pareto approach originally used in evolutionary algorithms (EA). The proposed modified particle swarm algorithm is used to build three hybrid EA-PSO algorithms to solve different multi-objective optimization problems. This algorithm and its hybrid forms are tested using seven benchmarks from the literature and the results are compared to the strength Pareto evolutionary algorithm (SPEA2) and a competitive multi-objective PSO using several metrics. The proposed algorithm shows a slower convergence, compared to the other algorithms, but requires less CPU time. Combining PSO and evolutionary algorithms leads to superior hybrid algorithms that outperform SPEA2, the competitive multi-objective PSO (MO-PSO), and the proposed strength Pareto PSO based on different metrics.

An FPGA Implementation of the LMS Adaptive Filter for Audio Processing

This paper proposes three different architectures for implementing a least mean square (LMS) adaptive filtering algorithm, using a 16 bit fixed-point arithmetic representation. These architectures are implemented using the Xilinx multimedia board as an audio processing system. The on-board AC97 audio codec is used for audio capture/playback, and the Virtex-II FPGA chip is used to implement the three architectures. A comparison is then made between the three alternative architectures with different filter lengths for performance and area. Results obtained show an improvement by 90% in the critical part of the algorithm when a hardware accelerator is used to perform it over a pure software implementation. This results in a total speed up 3.86times. However, using a pure hardware implementation results in a much higher performance with somewhat lower flexibility. It shows a speed up close to 82.6times over the software implementation

Effective memetic algorithms for VLSI design automation = genetic algorithms + local search + multi-level clustering

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35 for the VLSI circuit partitioning problem and 54 for the VLSI standard cell placement problem.

Attractor-repeller approach for global placement

Traditionally, analytic placement has used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together. The result is a placement with a great deal of overlap among the cells. To reduce cell overlap, the methodology iterates between global optimization and repartitioning of the placement area. In this work, we added new attractive and repulsive forces to the traditional formulation so that overlap among cells is diminished without repartitioning the placement area. The superiority of our approach stems from the fact that our new formulations are convex and no hard constraints are required. A preliminary version of the new placement method is tested using a set of MCNC benchmarks and, on average, the new method achieved 3.96% and 7.6% reduction in wirelength and CPU time compared to TimberWolf v7.0 in the hierarchical mode.

A first course in digital design using VHDL and programmable logic

Present industry practice has created a high demand for systems designers with knowledge and experience in using programmable logic in the form of CPLDs and FPGAs in addition to hardware description languages. Many universities offer this type of training in advanced digital engineering courses. This paper describes our experience in integrating VHDL and programmable logic devices based on Xilinx Foundation tools and Altera into a first course in logic design. In the main, student reaction to the course was positive. The course seems to have the right blend of being current (using VHDL and FPGAs) and being hands-on (using bread-boarding). We conclude by stating that in our experience, modeling using VHDL and mapping designs to FPGAs can be effectively integrated into a first course in logic design.

StarPlace: A new analytic method for FPGA placement

To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+. The star+ model is a variant of the well-known star model and is continuously differentiable - a requirement of analytic methods that rely on the existence of first- and second-order derivatives. Most importantly, with the star+ model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8-9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode.

Fast techniques for standby leakage reduction in MTCMOS circuits

Technology scaling causes subthreshold leakage currents to increase exponentially. Therefore, effective leakage minimization techniques must be designed. In addition, for a true low-power solution in system-on-chip (SoC) design, it has to be tightly integrated into the main design environment. This paper presents two design techniques to effectively solve the sleep transistor sizing and distribution problem in MTCMOS circuits. The introduced first-fit and set-covering approaches achieve lower leakage at an order of magnitude reduction in CPU time compared with other techniques in the literature. In addition, an automatic MTCMOS design environment is developed and integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design flow.