Mehdi Zamanian

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail. >

Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS

This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed in 130 nm CMOS.

Plasma charging effects on device degradation from via sputter etch

Inductively Coupled Plasma (ICP) and diode sputter etch processes for via filling technology were evaluated in view of the plasma and/or high field damage to the 7 nm gate oxide in both n- and p-channel MOSFETs using 0.35 micrometers CMOS technology. A number of sputter process conditions were considered including the substrate bias, gas flow, and sputter power to examine the threshold voltage instability, drive currents degradation and charge trapping in the gate oxide and the generation of Si/SiO2 interface traps. Via sizes ranging from 0.5 to 1.0 micrometers were studied for lower and tighter distributions of via resistance. A comparison between ICP and diode sputter processes showed better process robustness for ICP sputter etch than of the diode sputter process. Un- annealed and as processed devices showed as high as 20% change in threshold voltage (Vt) shift and 10% decrease in drive currents for the diode sputter process while the ICP process resulted in as low as 5% change in threshold voltage shift and less than 3% degradation in drive currents. Differences between n- and p-MOSFETs degradation were also observed. The possible process-induced device damage mechanisms will be discussed.