Francois Jacquet

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

An 8 Mbit DRAM design using a 1 Tbulk cell

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

An alpha immune and ultra low neutron SER high density SRAM

Terrestrial radiations, such as neutrons or alpha, create charges which, when collected by sensitive memory nodes, can destroy its stored information. Such a failure is called a soft error since only the data is destroyed while the circuit itself is not permanently damaged. Today, as the dimensions and operating voltages of semiconductor devices are continually reduced, the intrinsic SRAM sensitivity to ionizing radiations significantly increases. Whereas there is a linear and moderate increase on a per Mbit basis, the system SER significantly grows up together with the amount of SRAMs embedded in the chips. To meet the increasing need for both robust and highly integrated SRAMs, an original 3D memory device has been developed mixing SRAM and eDRAM capacitors. This memory cell, named rSRAM/spl trade/ cell (r standing for robust), has been validated through a testchip manufactured in a standard 120 nm CMOS technology.