Mehmet Uzunkol

Ultra Low-Loss 50-70 GHz SPDT Switch in 90 nm CMOS

This paper presents an ultra-low-loss 50-70 GHz single-pole double-throw (SPDT) switch built using a standard 90 nm CMOS process. The switch is based on λ/4 transmission lines with shunt inductors at the output matching network. The SPDT switch results in a measured insertion loss of 1.5-1.6 dB at 53-60 GHz and <; 2.0 dB at 50-70 GHz. The measured isolation is >25 dB, and the output port-to-port isolation is > 27 dB at 50-70 GHz. The measured P1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than -8 dB at 50-70 GHz. The active chip area is 0.5 × 0.55 mm2 and can be reduced in future designs by folding the on λ/4 transmission lines. To our knowledge, this paper presents the lowest insertion loss 60 GHz SPDT in any CMOS technology.

A 0.32 THz SiGe 4x4 Imaging Array Using High-Efficiency On-Chip Antennas

This paper presents a 0.32 THz 4x4 imaging array based on an advanced SiGe technology. Each pixel is composed of a high efficiency on-chip antenna meeting all metal-density rules, which is coupled to a SiGe detector and a low noise CMOS operational amplifier. A quartz superstrate is used on top of the imaging chip to improve the radiation efficiency. The array results in an average NEP of 34 pW/Hz 1/2 at an IF of 10-100 kHz for a detector bias current of 50-150 μA, a responsivity of 18 kV/W and a 3-dB bandwidth of 25 GHz. The power consumption is 2.4 mW/pixel. Extensive measurements are presented which show the challenges encountered in obtaining accurate measurements at THz frequencies using a quasi-optical set-up, and the decisions taken to quote the average NEP values.

140–220 GHz SPST and SPDT Switches in 45 nm CMOS SOI

This letter presents 140-220 GHz single-pole single-throw (SPST) and single-pole double-throw (SPDT) switches built using 45 nm semiconductor-on-insulator (SOI) CMOS technology. A tuned-shunt topology is used to minimize the insertion loss, and the transistor layout results in very low ground inductance and high isolation. The double-shunt SPST switch results in an insertion loss of 1.0 dB and an isolation of 20 dB, while the SPDT switches result in an insertion loss of 3.0 dB and an isolation of 20-25 dB, all at 180 GHz. The switches are well matched with a return loss at all ports greater than 10 dB at 140-220 GHz. The work shows that advanced CMOS nodes can be used for transmit-receive switches in emerging 140-220 GHz CMOS systems.

A 65 GHz LNA/Phase Shifter With 4.3 dB NF Using 45 nm CMOS SOI

This letter presents the first 45 nm CMOS SOI LNA/phase shifter for 60 GHz applications. The 3 b phase shifter is designed using a switched-LC approach and results in only 6 dB loss at 65 GHz. The LNA/phase shifter front-end results in a gain of 6.5 dB, a noise figure of 4.3 dB, and an input <;i>;P<;/i>;1dB of - 13.5 dBm (limited by the amplifier) with a power consumption of 15 mW. This work shows that advanced CMOS processes are essential for low power, medium linearity 60 GHz phased arrays.

Millimeter-Wave and THz Circuits in 45-nm SOI CMOS

This paper presents low-noise amplifiers (LNA) at 45¿C95 GHz, a frequency doubler at 180 GHz, active and passive mixers at 130¿C180 GHz fabricated in 45-nm Semiconductor-On-Insulator (SOI) CMOS process for digital and mixed-signal applications. The measured ft and fmax of a 30¡A1-¿Im transistor are 200 GHz at 0.3 mA/¿Im current density, referenced to the top metal layer. The measured gain and NF of LNAs are 15¿C11 dB and 3.3¿C6.0 dB at 45¿C95 GHz. The balanced doubler results in an output power of 1 mW and 8 dB conversion loss at 180 GHz. Passive double-balanced and active single-balanced mixers achieve conversion loss of 12¿C13 dB at 130¿C180 GHz, and 4 dB with 3-dB bandwidth of 145¿C161 GHz, respectively. This work shows that 45-nm SOI CMOS process results in state-of-the-art performance for millimeter-wave applications.

Design and Analysis of a Low-Power 3–6-Gb/s 55-GHz OOK Receiver With High-Temperature Performance

This paper presents an in-depth analysis of an SiGe BiCMOS on-off keying (OOK) receiver composed of a low-noise SiGe amplifier and an OOK detector. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. The LO leakage from the transmitter can also have a detrimental impact on the receiver sensitivity and should be minimized for best performance. The receiver consumes 11 mW, has a noise equivalent power of 5-10 fW/Hz1/2 at 55 GHz, and an instantaneous dynamic range of 27-30 dB. The OOK receiver achieves 6-Gb/s communication with a bit-error rate (BER) <; 10-12 at room temperature. Operation is also demonstrated up to 105°C at 3 Gb/s with a BER <; 10-12.

A Low-Noise 150–210 GHz Detector in 45 nm CMOS SOI

This letter presents a G-band detector in a 45 nm silicon-on-insulator CMOS technology. The measured detector responsivity is 3 kV/W at 170-180 GHz with a 3 dB bandwidth of 150-210 GHz. The detector results in a Noise-Equivalent-Power (NEP) of 8-10 pW/Hz1/2 at a bias current of 50-200 μA for an IF of 10 MHz and is well matched with an input return loss > 10 dB at 167-194 GHz. The responsivity and NEP values are close to the best SiGe detectors, and show that advanced CMOS nodes are suitable for ~ 200 GHz imaging arrays.

Design and characterization of a SiGe RFICs for millimeter-wave radiometers

This paper presents the design and characterization of SiGe RFICs for millimeter-wave radiometers. It is seen that SiGe technology results in high gain millimeter-wave amplifiers, high responsivity detectors and low overall 1/f noise, making it ideal for on-chip radiometers. Two example radiometer systems, one at W-band and one at D-band, are presented in detail.

Towards high-performance > 100 GHz SiGe and CMOS circuits

This paper presents SiGe and CMOS circuits with > 100 GHz operation. The goal is to show that SiGe can be used for imaging systems due to its low 1/f noise properties. A W-band SiGe imaging chip is presented with performance which is nearly as good as the best InP chips. Another goal is to show that deep-scaled CMOS can result in high performance amplifiers, detectors, and doublers at 90–110 GHz and at 180–220 GHz. The applications areas are in high data-rate communications, > 100 GHz automotive radars (140 and 220 GHz) and mm-wave imaging systems.

Millimeter-wave and terahertz sources and imaging systems based on 45nm CMOS technology

This paper presents the recent advances in sources and imaging arrays for >100 GHz applications. For sources, multiplier approach has recently demonstrated 1 mW of power at 200 GHz using 45 nm CMOS technology. For active imaging arrays, high-efficiency on-chip antennas coupled with low-noise CMOS SOI detectors are built at 300 GHz and 1 THz for low NEP systems.