Ozan Dogan Gurbuz

A 0.32 THz SiGe 4x4 Imaging Array Using High-Efficiency On-Chip Antennas

This paper presents a 0.32 THz 4x4 imaging array based on an advanced SiGe technology. Each pixel is composed of a high efficiency on-chip antenna meeting all metal-density rules, which is coupled to a SiGe detector and a low noise CMOS operational amplifier. A quartz superstrate is used on top of the imaging chip to improve the radiation efficiency. The array results in an average NEP of 34 pW/Hz 1/2 at an IF of 10-100 kHz for a detector bias current of 50-150 μA, a responsivity of 18 kV/W and a 3-dB bandwidth of 25 GHz. The power consumption is 2.4 mW/pixel. Extensive measurements are presented which show the challenges encountered in obtaining accurate measurements at THz frequencies using a quasi-optical set-up, and the decisions taken to quote the average NEP values.

A 0.39–0.44 THz 2x4 Amplifier-Quadrupler Array With Peak EIRP of 3–4 dBm

This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > 100 μW of power at 370-430 GHz. The amplifier-multiplier concept is proven on a 2×4 array, and it can be also scaled to any N×M array using additional W-band splitters and amplifiers.

A 60 GHz single-chip 256-element wafer-scale phased array with EIRP of 45 dBm using sub-reticle stitching

This paper presents a 60 GHz wafer-scale transmit phased-array with 256-elements spaced λ/2 apart in the x and y directions, and occupying an area of 4.14×4.2 cm2 (1740 mm2). The phased array is built using independent RF, transmission-line and control circuit blocks which are stitched together to form an aggregate chip which is much larger than a standard reticle (22×22 mm2). This method allows for a wafer-scale design and can be extended to any size and any shape (rectangular, hexagonal, etc.) up to the edge of the wafer. The blocks include high-efficiency on-wafer antennas, phased-array channels with 3-bits amplitude and 5-bits phase control together with an amplifier having an output power of +3 dBm at 60 GHz. Also, a highly redundant RF distribution network is synthesized from several stitched blocks for improved yield, and the control blocks have redundant SPI control and power strips, also for improved yield. The 256-element array results in a half-power beamwidth of 6° in the E- and H-planes, a directivity of 29 dB, and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of <;-25 dB. The measured EIRP is 45 dBm at 61 GHz and with a 3-dB bandwidth from 58 to 64 GHz. To our knowledge, this is the largest single-chip phased-array ever developed and allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together.

Spatially power-combined W-band power amplifier using stacked CMOS

A spatially power-combined CMOS SOI power amplifier at 94 GHz is reported. The CMOS chip contains a 2×4 array of pseudo-differential power amplifiers, and is integrated with a microstrip antenna array on a quartz superstrate. A 13-stage amplifier chain is implemented to provide gain, using stacked NFETs in a 45-nm CMOS SOI process. The amplifier array outputs a power of 24 dBm (250 mW) and the chip-quartz assembly radiates an equivalent isotropic radiated power (EIRP) of 33 dBm at 94 GHz. This is the highest radiated power reported from a Silicon CMOS active array transmitter at W-band, and the highest W-band output power from a single CMOS chip.

Transmission of Signals With Complex Constellations Using Millimeter-Wave Spatially Power-Combined CMOS Power Amplifiers and Digital Predistortion

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2 × 2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm.

A 60 GHz 64-element wafer-scale phased-array with full-reticle design

This paper presents the first large-scale wafer-scale phased-array at 60 GHz with 64-elements spaced λ/2 apart and occupying a full reticle area of 2.2×2.2 cm2. The transmit array includes high-efficiency on-wafer antennas, 3-bits amplitude and 5-bits phase control on each element, and a highly redundant RF distribution network for improved yield. It also includes redundant SPI control and power strips, also for improved yield. The 64-element array results in a half-power beamwidth of 12.5° in the E- and H-planes, a directivity of 23 dB and scans to +/- 55° in the E- and H-planes with near-ideal patterns and a cross-polarization level of >-25 dB. The measured EIRP is 38 dBm at 66 GHz, but this is currently being redone for improved accuracy. To our knowledge, this is the largest single-chip phased-array ever developed and paves the way to mm-wave large-scale (1000+ elements) phased-array systems.

Millimeter-wave large-scale phased-arrays for 5G systems

This talk will present our latest work on silicon RFICs for phased-array applications with emphasis on very large chips with built-in-self-test capabilities for 5G systems. SiGe is shown to be ideal for mm-wave applications due to its high temperature performance (automotive radars, base-stations, defense systems, etc.) and lower power consumption. These chips drastically reduce the cost of microwave and millimeter-wave phased arrays by combining many elements on the same chip, together with digital control and some cases, high-efficiency antennas. The phased-array chips also result in an easier packaging scheme using either a multi-layer PCB or wafer-level packages. We believe that this family of chips will be essential for millimeter-wave 5G communication systems.

A CMOS 45 GHz power amplifier with output power > 600 mW using spatial power combining

A single-chip 45 GHz power amplifier implemented in 45nm CMOS SOI is described, which feeds its RF output power to a 2×2 antenna array on an accompanying printed circuit board. The chip results in a maximum RF output power of 28 dBm (630 mW), and the system achieves a peak equivalent isotropic radiated power (EIRP) of 10 Watts (for a 2×2 antenna gain of 12 dB). The power amplifier is composed of 4 unit amplifier cells, each of which has pseudo-differential outputs. Stacking of 4 transistors was used in order to increase allowable voltage swings. The overall chip dimensions are 4.5 × 2.5 mm2. The DC power consumption was 4.9 W from 5.5 V and 4.0 V supplies, corresponding to a power-added efficiency of 13.5%.

60-GHz 64- and 256-Elements Wafer-Scale Phased-Array Transmitters Using Full-Reticle and Subreticle Stitching Techniques

This paper presents 60-GHz wafer-scale transmit phased arrays with 64- and 256-elements spaced λ/2 apart in the x- and y-directions, and occupying an area of 21.4 × 22 mm2 (471 mm2) and 41.4 × 42 mm2 (1740 mm2), respectively. The 64-element phased array is built as a complete reticle and includes 64 independent transmit channels with 5-b phase control, 3-b (9 dB) amplitude control, a saturated output power of 3 dBm at the antenna port, a 1-64 distribution network with redundant line amplifiers, and a high-efficiency on-chip antenna at each element. In addition, redundant serial digital interface and power strips, dual series metal-insulator-metal capacitors, and multiple RF inputs are employed for improved yield. The 256-element array uses the same phased-array blocks as the 64-element design, but is built using a subreticle stitching technique so as to result in a chip which is larger than the standard reticle size (22 × 22 mm2). The 64and 256-element arrays result in a half-power beamwidth of 12° and 6° in the E- and H-planes, a directivity of 23 and 29 dB, respectively, and scan to ±55° in the E- and H-planes with near-ideal patterns and a crosspolarization level of lesser than -30 dB. The measured equivalent isotropically radiated power (EIRP) of the 64-element array is 38 dBm at 62 GHz with a 3-dB bandwidth of 61-63 GHz, while that of the 256-element array is 45 dBm at 61 GHz with a 3-dB beamwidth of 58-64 GHz. A 1-4-Gb/s communication system is also demonstrated using the 64-element phased array up to ±45° scan angles, and at 4-, 30-, and 100-m ranges. To the best of our knowledge, this paper represents the first demonstration of large size (64and 256-element) phased-array transmitters on a single wafer.

-Band Spatially Combined Power Amplifier Arrays in 45-nm CMOS SOI

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5 × 4.5 mm2) containing eight-unit PAs was developed and its output was fed to a 2 × 2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2 × 8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the 2 × 2 and the 2 × 8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%.