Meng-Lin Hsia

An UHF Passive RFID Transponder Using A Low-Power Clock Generator without Passive Components

In this work, we propose a radio frequency identification (RFID) transponder operating in the UHF range. The RFID transponder encompasses the RF front-end circuit and signal processing unit. Of which, the RF front-end circuit consists of the voltage multiplier, voltage regulator, bias circuit, power on reset (POR), clock generator and ASK modulator/demodulator. This work proposes a ring oscillation scheme for the clock generator in the RF front-end circuit, which is capable of generating the two clock signals it requires without the use of the capacitor, resistor and inductor. Such scheme not only reduces the area it may require for the three kinds of passive components, it also reduces the power consumption. By using the TSMC 0.35-mum CMOS technology, the proposed RFID transponder with an area of 0.31 mm2 is implemented based on the ISO 18000-6 standard where the clock generator consumes only 0.4 muW.

Gender-to-Age hierarchical recognition for speech

In this work, a gender-to-age hierarchical analysis structure is proposed rather than directly classifying speech clips into gender and age categories. A two-stage Support Vector Machine (SVM) classifier is adopted to identify a female and male, and then conduct an age classification. To realize the gender recognition, the mean of the fundamental frequency and the standard deviation of the fast Fourier transform from speech clips are employed. Additionally, a part of 16 extracted speech characteristic parameters are used to understand human ages according to their genders. Notably, human utterance characteristics are considered to determine adequate speech parameters to minimize feature ambiguities among females and males under different ages. The experimental results demonstrate that the proposed gender-to-age hierarchical recognition scheme can achieve 17.9% accuracy-rate improvement in average, as compared to the results from the conventional direct classification scheme.

Passive RFID transponder with power-aware encryption

A passive RFID transponder with power-aware encryption is developed to address security under available power. This transponder includes an RF front-end module, a signal processing unit and a power-aware security module. In this power-aware security module, the Advanced Encryption Standard (AES) is adopted at 128 bits where the manners of encryption transformations are dynamically adapted according to available power. Additionally, serial input and output are implemented in the power-aware security module to minimize hardware and connection complexities. Particularly, varied frequencies and redundant bits are also employed in the encrypted data from AES to enhance security. As compared the conventional transponders, the proposed transponder can effectively use power to do and vary encryptions. Furthermore, this power-aware mechanism can be a plus to security.

A Multi-Band CMOS LC Quadrature VCO for GSM/DCS/DECT/WCDMA/Bluetooth Systems

In this work, a multi-band CMOS Voltage Control Oscillator (VCO) using the LC tank technique is developed to meet phase noise requirements of GSM, DCS, DECT, WCDMA(CDMA2000) and Bluetooth. To accomplish the multi-band receiving architecture at a low hardware cost, the proposed VCO based on switched capacitors and cross-coupled transistors without tail transistors is designed to yield quadrature output signals. Our Quadrature VCO (QVCO) fabricated by the TSMC 0.18um 1P6M CMOS technology is operated at 1V with a die size of 0.95mm2. At 600-kHz offset, the phase noises of the proposed QVCO are -124dBc/Hz, -122dBc/Hz, -125dBc/Hz, -118dBc/Hz and -124dBc/Hz at 0.9GHz, 1.8GHz, 1.9GHz, 2.2GHz and 2.4GHz, respectively. Therefore, the proposed QVCO is demonstrated to have sufficiently good performance for these standard applications.

Low-Complexity Inverse Transforms of Video Codecs in an Embedded Programmable Platform

This work presents an efficient low-complexity method to compute a 2-D inverse transform flexibly adapted to its end-of-block (EOB) point and corner coefficients. First, the EOB point is obtained from a bitstream or derived from the other parameters. Second, the values of bottom-left and/or top-right corner coefficients before an EOB point are verified as zero or not. Third, the operational mode, based on the EOB point and corner coefficient value(s), determines the reduced dimensional sizes of 1-D inverse transforms in the row and column. Additionally, the computational order of row-after-column or column-after-row is decided to minimize computational complexity. Finally, a 2-D inverse transform at the determined operational mode is computed using simplified 1-D inverse transforms in a row-by-row and column-by-column manner. Particularly, how to implement cycle-efficient structures of inverse transforms in an embedded programmable platform is investigated. Simulation results demonstrate that the proposed method has less computational complexity than conventional methods when executing 2-D inverse transforms at MPEG-2 and H.264/AVC video streams. Notably, the proposed method can reduce computational time required by conventional methods by 14.6%-92.9% at a fairly increased code size. Therefore, the proposed method is very suitable for various applications demanding low-complexity computations of inverse transforms.

Low-Complexity Encryption Using Redundant Bits and Adaptive Frequency Rates in RFID

In this work, we propose a low-complexity encryption used in a passive radio frequency identification (RFID) transponder. The proposed encryption functions by using redundant bits and adaptive frequency rates in the transponder to dynamically change the number of the transmitted bits and operation frequencies. The pseudorandom bit sequence is generated by the linear feedback shift register to represent the redundant bits. Additionally, the ring oscillator with a divider and a multiplexer produces a programmable operation frequency. Such approach not only protects the transmitted data under fairly low power consumption, but it also can integrate with the other encryption methods, such as the advanced encryption standard (AES) and the data encryption standard (DES), to further enhance security. Therefore, the encryption scheme proposed herein can be applied in various communication devices to achieve high-security and low-complexity performance

Acoustic field enhancement for a stereo headphone

In this work, acoustic field enhancement for a stereo headphone is developed based on sound image widening and deepening. In sound image widening, the correlation between left and right channels is effectively decreased by using decorrelator, adaptive-gain differential signal module and energy conservation module with consideration of psychoacoustic critical bands. In sound image deepening, acoustic echoes and shadowing in stereo channels are explored. Two delayed echoes are searched in all critical bands to find adequate locations under the criterion of the minimum inter-channel correlation coefficient. The experimental results reveal that the proposed method effectively reduces objective correlation of stereo channels and enhances sound image widening and deepening subjectively. Therefore, the acoustic field enhancement method proposed herein can fairly provide immersive, spatial, continuous stereo sounds for a user.

Low-power multiplier optimized by Partial-Product Summation and adder cells

This work presents a low-power multiplier using a Dynamic-Range Determination (DRD) unit and a modified Upper/Lower Left-to-Right (ULLR) structure in the Partial-Product Summation (PPS) unit. Prior to executing a multiplication, effective dynamic ranges of two input data are estimated by the DRD unit to determine that these input data with smaller and larger dynamic ranges are multiplier and multiplicand for Booth decoding, respectively. Such approach can exhibit that partial products in high precision have a high chance of being zero. Due to this phenomenon, the ULLR structure is modified by moving the correction bits from the upper part to the lower part of the PPS unit to reduce switching power. Additionally, various 10-transistor adder cells are investigated to find out the adequate ones in upper and lower parts of the PPS unit for power conservation. By using in-house cells and standard cells of the TSMC 1P6M 0.18-µm CMOS technology, the proposed and conventional multipliers are implemented and simulated by the Power-mill and Time-mill tools. The simulated results demonstrate that the proposed multiplier consumes the least power than the conventional ones in multimedia computing.

Rapid bit-error-rate measurements of infrared communication systems

In this work, we develop a method for rapid bit-error-rate (BER) measurements to reduce testing time of infrared communication systems. This method is to increase the probability of errors occurring in the communication system, which are caused by adding some special signals, such as DC offset noise and additive white Gaussian noise, inside the transmitter. The measured results are used to estimate the BER of the IrDA device at normal operation. Additionally, the relationship between the BER and the confidence level is explored to support the proposed rapid measurement. In our practical measurements of IrDA at 115.2 Kbps, measurement time for each testing device can be reduced from 12 hours to 1.45 seconds with a reduction of around 10/sup 5/ times. The proposed rapid measurement system has been successfully developed and can be easily applied to measure various optical communication systems at a low set-up cost.

Quality-preserved and low-complexity frequency-domain down-sizing method in a video decoder

This work is to explore a frequency-domain down-sizing method which preserves picture quality and consumes low complexity in a video decoder. The conventional frequency-domain down-sizing methods usually yield a drift error owing to frequency-domain coefficient truncation and motion compensation using small reference frames. The proposed method can overcome this drawback by using non-zero coefficient compensation and adaptive block-size decoding. In a Group of Pictures (GOP), an I frame and P frames close to the I frame are decoded at a full frame size and then are performed by downscaling. The motion vectors of the other P frames are pre-decoded first and then are analyzed to understand their referring relationship. Based on this relationship, the blocks which are referred and not referred by the other moving blocks are decoded at full and small block sizes, respectively. Additionally, B frames are decoded at an adaptive block size. The simulation results demonstrate that the proposed method can attain the same picture quality and 11%-29% complexity reduction than the conventional method conducting at a full frame size.