Menglian Zhao

ULTRA-LOW POWER BOOST CONVERTER WITH CONSTANT ON-TIME-BASED MPPT FOR ENERGY HARVESTING APPLICATIONS

An ultra-low power boost converter for energy harvesting applications is introduced in this brief. The idle power dissipation is reduced to 800 nW by using a novel output voltage detector (OVD) which is insensitive to temperature variation and process deviation. Furthermore, a constant on-time (COT)-based hysteretic burst mode controller with maximum power point tracking (MPPT) technique is developed to ensure high power efficiency for a wide input voltage range. After startup, the input voltage can be set as low as 30 mV. The whole system is designed and fabricated in SMIC 0.18 μm CMOS process, the end-to-end power efficiency of this converter can reach 49% at 350 mV input voltage and 65% at 750 mV input voltage.

An adaptive on-time controlled boost LED driver with high dimming ratio

A high efficiency high dimming ratio boost LED driver without color shift issue is presented in this paper. The boost converter is controlled by an adaptive on-time (AOT) controller, using improved control stratagem based on constant on-time (COT) control, so as to realize fast transient response to achieve high dimming ratio. With AOT control, the operation frequency maintains constant under continuous current mode (CCM) and the output voltage ripple could be reduced. In addition, Pulse frequency modulation (PFM) is implemented automatically under discontinuous current mode (DCM) to improve the system efficiency. The chip was designed and implemented in 1.5 μm bipolar-CMOS-DMOS (BCD) process. The simulation and experimental results showed that the minimum dimming on-time could be reduced to 1.2 μs, which means a dimming ratio of 2000:1 is available at dimming frequency of 400 Hz.

A novel capacitively-coupled instrumentation amplifier employing chopping and auto-zeroing

This paper presents a novel low power high precision instrumentation amplifier (IA) for general sensors. By using capacitively-coupled topology, wide input common-mode range, high gain accuracy and low power consumption is achieved. To reduce high output ripples caused by chopping technique and avoid noise aliasing effect due to auto-zeroing technique, these two techniques are employed simultaneously in this novel IA to alleviate their own adverse effects. The designed IA was implemented in SMIC 0.18μm CMOS process, and its core area is 0.28mm2. Simulations show that it consumes only 4.5μA current at 1V supply and the equivalent input noise power spectrum density (PSD) is 42.66nV/√Hz around 100Hz.

Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers

In this paper, two high-precision switched-opamp (SO) based ΔΣ modulators with ultra low figure-of-merit (FOM) are introduced respectively for bio-medical and audio applications. To save 50% power, both modulators adopt novel fully-clocked current mirror SOs with new bias circuits especially designed for SO. Besides, several measures are proposed separately in two modulators to ensure high performances. Both circuitries are implemented in 0.18µm CMOS. The modulator-I, for bio-medical applications, employs high density MOSCAPs to reduce chip area. Also, an innovative zero static power quantizer using MOSCAP-strings is developed to save up to 96% power and 69% area than traditional structure. With only 13µW power consumption at 1.0V supply voltage, it achieves 85dB peak-SNDR, 44.7fJ/conv.-step FOM for 10 kHz bandwidth. In the modulator-II, for audio applications, a novel 17-level scheme consisting of only nine comparators and two capacitor-strings is introduced to remove static power completely and save 40% chip area over the traditional quantizer. In addition, a dual cycle shift (DCS) DWA technique is introduced here to suppress in-band tone effectively. The modulator-II achieves 92dB peak-SNDR and 35.6fJ/conv.-step FOM with only 58µW power consumption at 0.9V supply voltage.

A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator

A 9µW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35µm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance, a novel resonator idea applicable to SO technique is adopted to realize a coefficient of 1/100 with 75% power and 70% area reduction over the conventional design. The FOM of the designed modulator is highest among the collected recent low power modulators.

Single-inductor dual-output converter with dynamic power distribution

A single-inductor dual-output switching converter was presented in this paper. This converter can be applied to solar-cell portable devices as battery power management system. Considering the limited power supplied by solar cells, two output channels, battery charging and power regulating, were designed for this converter. Controlled by it, the output electric energy could be dynamically distributed between two channels. The state-machine is used to decide the amount of energy delivered to each channel. The converter chip is designed in a 1.5µm BCD (Bipolar-CMOS-DMOS) technology. Simulation results showed that all main targets were well achieved1.

Low Voltage Low Power Current Mirror OTA for Sigma-Delta Modulator

Abstract-A low voltage low power class-AB operational transconductance amplifier (OTA) used in Sigma-Delta modulator is presented in this paper. To reduce the power consumption under low voltage, a current mirror topology with near rail-to-rail output swing is proposed. Its DC gain is enhanced by gain enhancement architecture without extra power consumption. Moreover, to achieve very low errors and smaller settle time, a novel switched-capacitor common-mode feedback (SC CMFB) circuit is introduced. Using 0.35 mum TSMC CMOS standard process, the OTA is designed to operate at 1.5 V supply voltage. For a 2.5 pF load capacitor the OTA achieves a DC gain of 60.58 dB, a GBW of 6.30 MHz and a slew rate of 3.24 V/ mus. The static power consumption is about 22 muW exclusive of that of CMFB circuit. It shows that the proposed OTA topology could be applied to low voltage low power switched- capacitor application.

A 0.9V 12-bit 200-kS/s 1.07µW SAR ADC with ladder-based reconfigurable time-domain comparator

This paper presents a SAR ADC for biomedical application, which has a strict limit on its power consumption. Thus, two techniques are introduced into its design: a novel ladder-based reconfigurable time domain (RTD) comparator is proposed to reduce the noise and to adjust power according to inputs automatically; and a novel clock distribution circuit is utilized to save more than 55% power consumption. The prototype chip is designed and fabricated in UMC 0.18μm technology. The simulation results show that with supply voltage of 0.9V, the ADC consumes 1.07μW at the sampling rate of 200kS/s. And the SNDR is 71.2 dB with 3.24kHz input sinusoid signal, showing the corresponding figure-of-merit of 1.8 fJ /conversion-step.

A 20-300mV transformer-based self-startup flyback converter with MPPT and ZCS control for thermoelectric energy harvesting

A novel high efficiency transformer-based flyback dc-dc converter with maximum power point tracking (MPPT) and zero current switching (ZCS) control is proposed in this paper. By adding a new primary side, the transformer works in flyback mode and the ordinary n-well process is used rather than twin-well. The startup process is divided into two modes: oscillation mode and constant duty-cycle flyback mode, greatly reduce startup time. The MPPT and ZCS control block work periodically, maximizing the energy delivered to the output capacitors. And the control methods are based on successive approximation digital logic. This converter is implemented in UMC 0.18μm CMOS process. Simulation results show that the current consumption of controller is only 0.6μA. Compared to previous work, the efficiency increase from 61% to 91% at VIN=300mV, and from 35% to 75% at VIN=20mV.

Self-adaptive window control technique for hysteretic buck converter with constant frequency

A hysteretic buck converter with self-adaptive window controller is presented in this paper. Since the switching frequency of conventioal hysteretic buck converter varies with the input voltage and load current, which might result in severe Electro-Magnetic Interference (EMI), a self-adaptive window control technique is proposed to tackle this problem. The proposed converter is design and fabricated in TSMC 0.35 μm CMOS process. Simulation and experiment results show that the switching frequency of this converter is held a near constant value when input voltage or load current changes.