Qing Liu

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L_G) of 20nm and BOX thickness (T_BOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (I_eff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (I_off) of 100nA/μm and V_dd of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low A_Vt (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.

UTBB FDSOI scaling enablers for the 10nm node

UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.

Enabling epitaxy on ultrathin implanted SOI

In Fully Depleted Silicon On Insulator (FDSOI) transi stors, the channel thickness is being scaled down with the gat length to insure a good electrostatic control of the gate ove r th channel. Typically for the 20nm node, the transistor integri ty is maintained by keeping the channel thickness below 6nm [1]. Thi s downscaling raises several technological challenges , especially when using an integration scheme in which extensions are implanted before the Raised Source and Drain (RSD) growth (Fig. 1). The challenge lies in finding a viable tradeoff between amorphization and high dopant concentration within t e film. In this paper we present what are the main physical lim itations when implanting the SOI, as well as an efficient way to a lleviate them.