Mengxin Liu

Predictive As-grown-Generation (A-G) model for BTI-induced device/circuit level variations in nanoscale technology nodes

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer-level test scheme for parameter extraction is developed, reducing test time to 1 hour/device and significantly improving the efficiency for variability tests of nanoscale devices. The model is implemented into a commercial simulator and its applicability for circuit level simulation is demonstrated.

Study of the SEU Effect Mechanism on SOI PMOS by 2-D Simulation

2D device simulation with an ideal condition is used to study the mechanism for single-event upset (SEU) of SOI pMOS, which can be more significant in SRAM when gate length is scaling down. The mechanism can be associated with displacement current. Displacement currents across the box layer can be induced as charge is generated in the SOI substrate by an ion strike. It perturbs the electric fields in the substrate near the oxide/substrate interface, thus an abnormal current is observed in drain. The displacement current is related to the box layer thickness, the substrate doping species and concentration, also the drain area. Therefore all this parameter is critical in the design of SOI SRAM ICs

A radiation hardened SRAM cell design in PD-SOI CMOS technology

A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.