Jinshun Bi

Single- and Multiple-Event Induced Upsets in

Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are experimentally demonstrated by generating current transients in the access transistors of the memory cells. The relationship between the single-event upset threshold of the RRAM and the applied voltage is exponential, which is verified using TPA laser analysis and heavy-ion irradiation. Multiple-Event Upsets (MEUs) also occur, where individual ions incrementally change the RRAMs resistance until their cumulative effect causes an upset. Single-event models are presented that allow direct correlation of the voltage across the RRAM, caused by the ion-generated current transient, and the change in RRAM resistance. The RRAM is vulnerable only in the high resistance state, when a voltage capable of writing to the cell is applied to the bit line. This is approximately 0.5% of the memory elements operation time, leading to relatively low projected upset rates.

{\rm HfO}_2/{\rm Hf}

This paper investigates total-ionizing dose effects on the electrical characteristics of HfO2/Hf-based bipolar resistive-random-access-memory (RRAM) devices. 10-keV x-ray irradiation does not cause significant changes in resistance at levels up to 7 Mrad( SiO2). Excess carriers generated by x-ray irradiation in the HfO2 layer recombine or are trapped at defect sites in the HfO2 layer or at interfaces between layers. They have no effect, however, on the conductive path of the RRAM devices. 1.8 MeV proton irradiation causes resistance degradation through simultaneous introduction of oxygen vacancies and displacement damage. TRIM simulations are used to explain the physical mechanisms of the radiation-induced damage. The devices are promising for radiation-hardened memory applications.

1T1R RRAM

This paper presents a new SEU-tolerant latch design based on Quatro and NMOS feedback transistors. By using these feedback transistors, the SEU susceptibility is decreased because of the cutoff feedback loop. Simulation results demonstrate that the proposed design is immune to static single node upsets. The proposed latch and the reference Quatro were designed and fabricated on a 130 nm process. The test chip was exposed to heavy ions at the TAMU Cyclotron facility. The testing results show that the proposed design has a higher upset LET threshold and lower cross-section when compared to the reference latch. Its lower SEU vulnerability comes with small area penalty.

The Impact of X-Ray and Proton Irradiation on

A new model for assessing NBTI and PBTI induced time-dependent variability under practical operation workloads is proposed. The model is based on a realistic understanding of different types of defects and has excellent predictive capability, as validated by comparison with experimental data. In addition, a new fast wafer-level test scheme for parameter extraction is developed, reducing test time to 1 hour/device and significantly improving the efficiency for variability tests of nanoscale devices. The model is implemented into a commercial simulator and its applicability for circuit level simulation is demonstrated.

{\rm HfO}_2/{\rm Hf}

The effects of X-ray and proton radiation on a LiNbO2 analog memristor are investigated by I-V hysteresis, Electrochemical Impedance Spectroscopy, low-frequency AC voltage, and X-ray diffraction analysis. Both electrical and structural characterization of an irradiated memristor show that irradiation leads to an increased level of defects in the LiNbO2 crystalline lattice. These radiation-induced defects facilitate faster lithium movement as shown by electrochemical impedance spectroscopy measurements on the as-grown and irradiated memristor. X-ray radiation improves ionic motion in the bulk of the device and increases the ionic resistance at the LiNbO2-metal interface. In the case of proton radiation, the memristance response improves due to an increase in ionic motion in the bulk and at the interfaces. It is also shown by Monte Carlo simulations that proton irradiation of LiNbO2 results in structural damage, which was verified experimentally by an X-ray diffraction study.

-Based Bipolar Resistive Memories

The neutron-induced single-event-transient (SET) response of 22-nm technology ultrathin-body fully-depleted silicon-on-insulator transistors is examined. Simulation results show that the impacts of ground plane doping and quantum effects on SETs are relatively small. The SET characteristics and collected charge are strike-location sensitive. The most SET-sensitive region in ultrathin-body fully-depleted SOI transistors is located near the drain region. The transient current peak is strongly affected by substrate bias. In contrast, the total collected charge depends only weakly on substrate bias. Circuits that are sensitive to total collected charge (e.g., SRAMs) may not be influenced by substrate bias, but substrate bias will impact the SET sensitivity of combinational logic.

An Area Efficient SEU-Tolerant Latch Design

A novel radiation-hardened-by-design (RHBD) structure to reduce the single event transient (SET) amplitude in analog circuits is presented in this paper. This structure features an SET isolation technique, which contains a sensor and a switch. The sensor turns off the switch when it detects a voltage transient at the sensitive node, in which case the core circuit is temporarily isolated from the output. Once the voltage at the sensitive node recovers, the sensor turns on the switch again in order to connect the core circuit to the output. This RHBD technique was validated based on a typical bandgap reference circuit, which was fabricated in the IBM 130 nm technology. The simulation results demonstrated a significant reduction in the SET amplitude, which was further verified with the pulsed laser. The additional sensor and the switch in the circuit only produce a minor amount of additional power dissipation if they are properly chosen. The area overhead is rendered negligible by means of selecting the appropriate sizes of transistors for the RHBD structure.

Predictive As-grown-Generation (A-G) model for BTI-induced device/circuit level variations in nanoscale technology nodes

Charge trapping in the buried oxide can lead to serious back-channel leakage and make SOI (Silicon-on-Insulator) transistors more sensitive to total dose radiation. In this paper, a new DSOI (Double SOI) transistor is proposed, which utilizes the method of back-gate biasing to force an external electric field, and then depress the back channel formation during total dose irradiation. The simulation and testing results both indicate that, for a given structure, when a -3V bias is applied to the back-gate, the DSOI transistor can tolerant a total dose radiation of 500k rad(Si). This methodology fits all kinds of SOI MOSFETs, especially for the Fully-Depletion SOI transistors. With commercial (not especially hardened) buried oxide, DSOI device can have better radiation hardening performance than its both companions - FDSOI and PDSOI transistors.

Radiation Effects on LiNbO

3D fully-depleted silicon-on-insulator (FDSOI) n-channel transistor model is constructed by the accurate calibration between process information from OKI and Synopsys TCAD tool. Single-event-effect (SEE) simulations are conducted based on the 3D model to evaluate the collected charge from different heavy ion strike locations. The channel is the most SEE sensitive region along channel length direction in terms of the collected charge. The TCAD simulations of the collected charge along channel width direction are constrained by the boundary condition. This paper provides the guide for the SEE hardening improvement of the FDSOI process and device structure.

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The shallow trench isolation (STI) y-stress effect on deep submicron PDSOI MOSFETs was studied. Instance parameters SAy, SBy and model parameters a1, a2, b1, b2 were proposed to build a compact model for this effect. This model can be easily implemented in the SOI MOSFET compact model like BSIMSOI model. By using this model, we can simulate the STI y-stress effect well, especially for the changes of Idsat and Vtlin.