Michael A. Gaynes

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

Evaluation of contact resistance for isotropic electrically conductive adhesives

Electrically conductive adhesives are discussed and studied with ever-increasing interest as an alternative to solder interconnection in microelectronics circuit packaging. A similar level of scrutiny that is used to evaluate contact resistance performance for interconnections made with solder and separable connectors is necessary for electrically conductive adhesives. Experience with solder interconnection and separable connectors shows low initial contact resistance of less than 10 m/spl Omega/ when bulk conductor material is minimized in the measurement scheme. Stability is typically determined to be less than a 5-10 m/spl Omega/ change as a function of stress. The main intent of this study is to characterize the electrical contact resistance performance of joints made with isotropic electrically conductive adhesives. A copper comb pattern test vehicle was designed and fabricated using 0.25-mm thick lead frame material. The plating finishes that were applied to the copper substrate included a palladium alloy, gold, tin, and nickel. Test samples were made with several electrically conductive adhesives. Samples consisted of two comb patterns bonded to each other making a gang of 40 lap joints. Variables from circuit packaging such as coefficient of thermal expansion mismatches are purposely avoided in this study. Contact resistance measurements were made initially and as a function of time during environmental tests. Stresses included thermal cycling, thermal aging, and temperature and humidity conditioning. The stability of electrical contact resistance is shown to be influenced by both plating metallurgy and the conductive adhesive itself. Contact resistance equivalent to solder is possible with some electrically conductive adhesives on appropriate metallurgical finishes. Mechanically, adhesive joints are less robust than solder joints, and therefore care must be taken to eliminate or minimize the effects of mechanical loading. >

Design and optimization of pin fin heat sinks for low velocity applications

In a number of electronic cooling applications, the air flow velocity and direction are not very well defined or controlled. In these applications, pin fin heat sinks are widely used because they are not sensitive to air flow direction. A study was undertaken to optimize the design of pin fin heat sinks for use in low velocity applications where there is plenty of open space around for the air to bypass the heat sink, if it encounters high pressure drop across it. The goal of this study was to maximize the thermal performance and keep the design such that it is easily manufacturable to keep the cost low. A special test fixture using a heat flux meter was designed to test the heat sinks for thermal performance. Several aluminum pin fin heat sinks having a 25/spl times/25 mm base size, heights from 5 to 25 mm, pin arrays of 4/spl times/4 to 8/spl times/8, and pin fin cross sections from 1.5/spl times/1.5 mm to 2.5/spl times/2.5 mm were fabricated and tested for thermal performance. Some of the commercial aluminum heat sinks with various surface finishes (such as black anodized, gold chromated, clear anodized and untreated) were also evaluated to determine the effect of surface treatment on thermal performance. The heat sink tester and the test data for the heat sinks used in this optimization study are reviewed in this paper. The results show that it is possible to design an optimum pin fin heat sink for any flow situation. However, it is not realistic to have several heat sink designs to cover various applications. In low velocity (about 1 m/s or less) open flow situations, the best compromise for pin fin heat sink with about 25/spl times/25 mm base size and heights up to 15 mm is the 6/spl times/6 pin fin configuration with fin cross-sections of 1.5/spl times/1.5 mm.

Server liquid cooling with chiller-less data center design to enable significant energy savings

This paper summarizes the concept design and hardware build efforts as part of a US Department of Energy cost shared grant, two year project (2010-2012) that was undertaken to develop highly energy efficient, warm liquid cooled servers for use in chiller-less data centers. Significant savings are expected in data center energy, refrigerant and make up water use. The technologies being developed include liquid cooling hardware for high volume servers, advanced thermal interface materials, and dry air heat exchanger (chiller-less with all year “economizer”) based facility level cooling systems that reject the Information Technology (IT) equipment heat load directly to the outside ambient air. Substantial effort has also been devoted towards exploring the use of high volume manufacturable components and cost optimized cooling designs that address high volume market design points. Demonstration hardware for server liquid cooling and data center economizer based cooling has been built and is operational for a 15 kW rack fully populated with liquid cooled servers. This design allows the use of up to 45 °C liquid coolant to the rack. Data collection has commenced to document the system thermal performance and energy usage using sophisticated instrumentation and data collection software methodologies. The anticipated benefits of such energy-centric configurations are significant energy savings at the data center level of as much as 30% and energy-proportional cooling in real time based on IT load and ambient air temperatures. The objective of this project is to reduce the cooling energy to 5% or less of a comparable typical air cooled chiller based total data center energy. Additional energy savings can be realized by reducing the IT power itself through reduced server fan power and potentially less leakage power due to lower device temperatures on average for most locations. This paper focuses on the server liquid cooling, the rack enclosure with heat exchanger cooling and liquid distribution, and the data center level cooling infrastructure. A sample of recently collected energy-efficiency data is also presented to provide experimental validation of the concept demonstrating cooling energy use to be less than 3.5% of the IT power for a hot summer day in New York.

Underfill selection strategy for Pb-free, low-K and fine pitch organic flip chip applications

The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits long term reliability testing of module hardware for every available underfill. A sequential three phase selection strategy is used to characterize and systematically eliminate undesirable candidates and to identify the few favorable underfills that have a high probability of successfully meeting module reliability requirements. The process includes use of industry practices as well as internally developed characterization methods. From an initial list of 20, the selection process identified five underfills for package qualification testing

Experimental investigation of dust particle deposition in a turbulent channel flow

Abstract An experimental set-up was designed, constructed, and used to study the wall deposition rate of particles in a turbulent channel flow. Deposition velocities for two classes of particles, namely, spherical glass particles with diameters of 5–45 μm, and five compact dust components in the size range of 1–10 μm were studied. The particle concentration at the test section was measured with the aid of an isokinetic probe. The particles were deposited onto a flat gold plate covered with a thin film coating. The coating was used to reduce the effect of particle bounce from the surface. The statistics of deposited particles were analyzed by an image processing technique which counts and sizes the particles. The deposition rate of spherical particles was found to increase with diameter. The deposition velocities for compact dust components were found to closely resemble those of equivalent spherical particles. The measured deposition velocities were in good agreement with the available experimental data and the empirical model.

The over-bump applied resin wafer-level underfill process: Process, material and reliability

The over bump applied resin (OBAR) process is a wafer-level underfill (WLUF) process in which a filled resin is applied over the bumps of a wafer and, dried. The wafer is diced into coated chips which are aligned and joined to a substrate resulting in an underfilled flip chip package. This process has been evaluated by IBM on several test vehicles in close cooperation with Henkel (formerly Abelstik) who developed a material specifically to fit this process. The critical steps to make this technology work are alignment of OBAR coated chip to a substrate, elimination of significant voids, formation of a fillet with appropriate shape and size, fluxing and solder joining. The reliability of the material was evaluated after capping and BGA (Ball Grid Array) attach through JEDEC level 3 preconditioning followed by DTC (deep thermal cycling), T&H (temperature and humidity), and HTS (high temperature storage). While some improvements are still needed, the OBAR process has been shown to be a viable alternative to capillary underfill application.

Experimental characterization of an energy efficient chiller-less data center test facility with warm water cooled servers

Typical data centers utilize approximately 50% of the total IT energy in cooling of the server racks. We present a chillerless data center where server-level cooling is achieved through a combination of warm water cooling hardware and re-circulated air; eventual heat rejection to ambient air is achieved using a closed secondary liquid loop to ambient-air heat exchanger (dry-cooler). Several experiments were carried out to characterize the individual pieces of equipment and data center thermal performance and energy consumption. A 22+ hour experimental run was also carried out with results indicating an average cooling energy use of 3.5% of the total IT energy use, with average ambient air temperatures of 23.8°C and average IT power use of 13.14 kW.

Particle detachment mechanisms from rough surfaces under substrate acceleration

Particle removal mechanisms due to an accelerating substrate from rough surfaces are studied. The rough surface is modeled by asperities all of the same radius of curvature and with heights following a Gaussian distribution. The Johnson-Kendall-Roberts (JKR) adhesion model is used and the procedure for analyzing the particle pull-off force is described. The theory of critical moment, in addition to the sliding and lifting detachment models, is used, and the critical substrate accelerations for particle removal are evaluated and discussed. The model predictions for aluminum and glass particles are also compared with the experimental data and reasonable agreement is observed. The application of the results to surface-cleaning equipment is discussed.

Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging

We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90°C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 × 13 mm and the test substrate was 42.5 × 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of −55 to 125°C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150°C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental stress. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.