Michael A. Kinch

The effect of low temperature annealing on defects, impurities, and electrical properties of (Hg,Cd)Te

Many methods for the preparation of (Hg,Cd)Te alloys rely on a low temperature processing step to convert the as‐grown p‐type material to n‐type, or to otherwise adjust the concentration of native acceptors. During this anneal, tellurium precipitates in the material are annihilated by in‐diffusing mercury, resulting in a substantial multiplication of dislocations. For substantially long anneals (>1 day at 270 °C) the depth of the p–n junction is found to vary as the square root of the anneal time and inversely as the square root of the excess tellurium concentration. Rapidly diffusing impurities such as silver are gettered out of the skin and into the remaining vacancy‐rich core. The kinetics of these processes are analyzed for self‐diffusion on the metal sublattice involving only vacancies, only interstitials, and for a mixed vacancy–interstitial model. Comparison with experimental data shows best agreement with the mixed interstitial–vacancy model.

Hg0.7Cd0.3Te charge‐coupled device shift registers

Eight‐bit CCD shift registers with 10‐μm‐long electrodes have been successfully fabricated on n‐type Hg0.7Cd0.3Te and operated between temperaures of 77 and 140 K. At 77 K, a charge transfer efficiency of 0.996 was obtained under four‐phase operation between 1 and 100 kHz clock frequencies. The input signal was provided by pulsing an input gate beyond the tunnel breakdown limit during the on‐time of the phase‐one potential well. Signal was detected using a floating‐gate output followed by correlated double sampling. The size of the signal is in agreement with predictions.

Interface properties of HgCdTe metal‐insulator‐semiconductor capacitors

The conductance method has been used to measure the density of interface states of the ZnS/Hg0.775Cd0.225Te metal‐insulator‐semiconductor (MIS) system with three different HgCdTe surface treatments. It is found that the density of fast interface states increases from ∼1011 eV−1 cm−2 at the conduction‐band minimum to ∼1013 eV−1 cm−2 near the valence‐band maximum. In addition, the interface states located in the lower part of the band gap communicate with the valence band so efficiently that the effective band gap is reduced. Our observations explain why the p‐type MIS photodiode is superior to the n‐type version in terms of breakdown voltage and storage time.

The MIS physics of the native oxide–Hg1−xCdxTe interface

Several key aspects of HgCdTe metal–insulator–semiconductor (MIS) device physics affecting the interpretation and analysis of admittance‐voltage data are discussed. The effect of degenerate statistics on the capacitance–voltage (C–V) characteristics of n‐type devices biased into accumulation and p‐type devices biased into inversion is demonstrated experimentally on MIS test devices with native oxide interfaces. Theoretical calculations using degenerate statistics and the k⋅p approximation are shown to predict the observed C–V behavior. Tunneling via Shockley–Read levels as it affects thermal equilibrium measurements of admittance‐voltage data is compared for the cases of p‐type and n‐type devices. Inversion layer quantization effects are observed in p‐type device tunneling phenomena, while n‐type devices exhibit tunneling behavior which is very sensitive to band‐gap states near the surface. Oscillations in conductance–voltage (G–V) data on p‐type devices are attributed to inversion layer quantization effects while the droop in low‐frequency G–V data on anodic oxide interface devices on n‐type material is attributed to a high density of subsurface band‐gap states introduced during the anodic oxide growth process. Multiple flatband effects in anodic oxide MIS devices with opaque and transparent gate regions can be induced by visible light exposure which creates a lateral nonuniformity in fixed charge at the oxide–HgCdTe interface.

HgCdTe charge-coupled device technology∗

Abstract Charge-coupled device action has been demonstrated for the first time in the variable bandgap alloy Hg 1−xCd x Te. 16-bit shift registers have been fabricated on 0.25 eV n -type material with a charge transfer efficiency of 0.9995. The mode of operation of these devices is described and their performance compared to simple CCD theory as applied to this narrow-gap infrared sensitive material. Supporting data on singlelevel MIS devices is presented to indicate the validity of our device analysis and the potential of this technology for future focal-plane applications.

Method of fabricating a narrow band-gap semiconductor CCD imaging device

A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Observation of a new gettering mechanism in (Hg, Cd)Te

Abstract A new gettering mechanism is proposed for substitutional impurities which diffuse by an interstitial process. In this mechanism, an externally imposed gradient of self interstitials generates a gradient in impurity interstitials leading to the segregation of fast diffusing impurities to low interstitials, high vacancy regions. Data are presented to support this model in (Hg, Cd)Te alloys, as well as explicitly rule out gettering by dislocations, by segregation to precipitates, or by enhanced solubility arising from the interaction of the impurity with a varying Fermi level.

Increased charge capacity in breakdown‐limited metal‐insulated semiconductor Hg1−xCdxTe devices using a ramped gate voltage

The useful charge capacity of a metal‐insulated semiconductor (MIS) device can be increased by utilizing a ramped‐gate‐voltage mode of operation. The ramping technique is demonstrated on 4.5 and 9.4‐μm long‐wavelength cutoff HgCdTe MIS devices measured at 80 K with a 300‐K background through ≃20° field of view and ?25% quantum efficiency. The gate voltage is ramped to increase the MIS well capacity at a rate slightly faster than the rate of photogenerated charge buildup in the inversion layer. The 4.5‐μm device achieved a storage capacity of greater than 3.7×10−7 C/cm2 (≳45 ms storage time), while the 9.4‐μm device achieved a storage capacity of 1.7×10−7 C/cm2 (300 μs integration time). The respective storage capacities demonstrated for these two wavelength bands are 3.5 and 17 times larger than obtained by the conventional pulsed‐gate technique.

HgCdTe Charge-Coupled Detectors (CCD)

CCD shift registers have been investigated in 4.4 pm HgCdTe for time delay and integrate (TDI) enhancement of responsivity and signal to noise ratio and for multiplexing a number of TDI shift registers. CCD linear arrays and area arrays have been operated from 77K to 140K cooling and from 50 kHz to above 1 MHz. Charge transfer efficiency (CTE) has been measured to 0.9999 on a 32 stage four phase p channel device. Infrared sensitivity measure-ments show, D* values above 1012 cmHz1/2/W for full TDI enhancement of32. TDI has been demonstrated utilizing focused laser illumination scanned synchronously with the clocked charge. Sensitivity and noise analyses have been made to show limits of detection for multiplexed arrays.