Michael A. Turi

Low power SRAM cell design for FinFET and CNTFET technologies

Implementations of SRAM cells in FinFET and carbon nanotube FET (CNTFET) technologies are presented in this paper. The International Technology Roadmap for Semiconductors has identified these technologies as likely candidates to replace bulk CMOS. Leakage current is one of the major contributors in the power consumption in SRAM arrays; FinFETs have been shown to greatly reduce leakage current. The FinFET memory cells are presented. These cells dissipate 0.49 µW of static power. The CNTFET memory requires 0.195 µW of static power. In current synthesis processes Metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. This CNTFET memory with metallic tolerance dissipates 0.21 µW of static power.

High-Performance Low-Power Selective Precharge Schemes for Address Decoders

Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the AND-NOR decoder is 80.8% of the nor decoder delay.

Performance-power tradeoffs of 8T FinFET SRAM cells

We present eight eight-transistor (8T) FinFET SRAM cells which differ in back-gate connections and swing of the Read-line input. These schemes are evaluated in terms of leakage current, delay, read and write energy dissipation, and static noise margin (SNM) for 16 bits by 16 words (16×16) and 32 bits by 1024 words (32×1024) SRAM arrays. Performance is compared between the 8T schemes and two well-performing six-transistor (6T) SRAM cells. Overall, the 8T-SRAM schemes perform better than the 6T schemes primarily because leakage current is reduced by low-power schemes that reverse-bias the back-gates of the cross-coupled inverters without an adverse impact on the read speed. This is especially true for larger SRAM arrays, e.g. 32×1024. For a 32×1024 SRAM array, the best performing 8T scheme, Low-Power Inverters (LP_INV), has an energy-delay product that is 87.3% less than the best-performing 6T scheme, Low-Power (minimum-sized) (LP6).

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells

An in-depth study of the static power consumption in 6T and 8T SRAM cell designs based on 32nm CMOS, FinFET and CNTFET technologies is presented. In addition to the inverter leakage currents, memory cells that are not active when write or read operations occur draw current from/to the bus drivers increasing the total standby power consumption. The FinFET schemes yield substantially lower write (1023.5 pA) and read (522.5 pA) leakage currents in 8T cells, which are 10.4% and 4.4% of the amount in CMOS 8T cells. A CNTFET 6T cell consumes 1.9% and 2.8% of the leakage current drawn by a CMOS 6T cell for write and read.

Reducing power in memory decoders by means of selective precharge schemes

Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.

FinFET 3T and 3T1D dynamic RAM cells

In this study we present 3T and 3T1D DRAM cells designed using FinFET technology. Overall, the 3T DRAM cell has a 43.6% faster write speed than the 3T1D cell and uses less dynamic current (30.4% less write current and 14.6% less read current). The FinFET 3T1D DRAM cell offers a 16.7% faster read speed and 48.6% less read leakage current than the 3T1D cell. The 3T DRAM cell offers less variation in delays, up to 37% less than the 3T1D cell for write delay, due to parameter corner simulations. Overall for a system, the 3T FinFET DRAM cell is more promising due to its low dynamic current and significantly shorter write speed which leads to a smaller maximum delay.

An evaluation of 6T and 8T FinFET SRAM cell leakage currents

We present six- and eight-transistor (6T, 8T) FinFET SRAM cell schemes using shorted gate (SG) and low power (LP) FinFET configurations and comprehensively evaluate their leakage currents. FinFETs provide significantly lower leakage current and higher on-current than bulk-CMOS transistors and this allows 8T FinFET SRAM schemes to greatly outperform 8T 32nm CMOS SRAM cells. Reverse-biasing the back gates of the cross-coupled inverter FinFETs reduces leakage current by up to 97%; the largest reduction is obtained with n- and p-back gate biases of -0.2V and VDD+0.2 V, respectively. This reverse-biasing also minimizes leakage variation due to parameter and temperature variations. Leakage current and read speed are chiefly responsible for SRAM energy consumption. The 6T Low-Power FinFET scheme uses these configurations and has the lowest leakage; however, 8T SRAM schemes perform better than 6T SRAM schemes since leakage current can be reduced by low-power schemes that reverse-bias the cross-coupled inverter FinFET back gates without reducing read speed or read static noise margin. The 8T Low-Power Inverters (LP_INV) scheme has low leakage and performs best with an energy-delay product up to 60% less than the standard 8T Shorted Gate (SG) FinFET scheme and up to 62% less than the best-performing 6T FinFET scheme.

Decreasing energy consumption in address decoders by means of selective precharge schemes

This paper presents and evaluates three novel memory decoder designs which reduce energy consumption and delay by using selective precharging. These three designs, the AND-NOR, Sense-Amp, and the AND decoder, range in selectivity and select-line swing; these schemes charge and discharge fewer select-lines. This in turn consumes less energy than nonselective address decoders which charge and discharge all select-lines each cycle. These three decoding schemes are comprehensively simulated and compared to the conventional nonselective NOR decoder using 65nm CMOS technology. Energy, delay, and area calculations are provided for all four 4-to-16 decoders under analysis. The most selective AND decoder performs best and dissipates between 61% and 99% less (73% less on average) and the selective Sense-Amp decoder performs only slightly worse by dissipating between 58% and 75% less (66% less on average) energy than dissipated by the NOR decoder. The AND-NOR decoder dissipates between 15% less and 20% more (6% more on average) energy than dissipated by the NOR decoder. In addition, the AND decoder is 7.5% and the Sense-Amp decoder is 5.0% faster than the NOR decoder, however, the AND-NOR decoder is 1.7% slower than the NOR decoder.

High-performance low-power AND and Sense-Amp address decoders with selective precharging

This paper presents and evaluates two novel address decoding schemes that use selective precharging, the sense-amp and the AND decoders, in comparison to the conventional NOR decoder. Simulations for all three designs are performed using 65 nm CMOS technology and the delays of all three decoders are set to 120 ps for a common base comparison. The most selective AND decoder performs best and dissipates between 0.17% and 43.17% (29.29% on average) and the selective Sense-Amp decoder dissipates between 28.81% and 48.33% (39.96% on average) of the energy dissipated by the nonselective conventional decoder.

An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice

We present an algorithm for generating Spice netlists with varied parameters/variables in order to support Monte Carlo simulations. A number of data structures are required to randomly or pseudo-randomly vary transistor parameters or simulation parameters/variables. This algorithm ensures that Spice sub-circuits and transistor fingers are expanded so that every transistor and transistor finger of the circuit is independently varied. Some versions of Spice do not have built-in support of Monte Carlo simulations. Therefore, this algorithm can enable engineers operating these Spice versions to generate netlists for executing Monte Carlo simulations. This is important since Monte Carlo simulations are commonly used to test the performance or operation of a circuit affected by parameter variations caused during the manufacturing process.