Michael Dossis

A Web Service to Generate Program Coprocessors

The design and implementation of today’s complex embedded systems including custom hardware and software is still to a large extent based on a collaboration of heterogeneous, semi-manual and often poorly inter-connected design methods and tools. This usually results in repetitive and longer development cycles. This paper describes an intelligent web service to automatically produce non-standard and custom hardware description code, including its memory and system interfaces from abstract, executable specification (unaltered program) code, via intelligent web interface and intelligent human-web interactions. Provably-correct hardware compilations are performed on selected high-level program subroutines by employing logic programming techniques and an intelligent inference engine. The intelligent inference engine is invoked automatically within the processes of the implemented high-level synthesis compiler. The proposed methodology and implemented tools are proven applicable and successful by evaluating results from implementation of linear as well as repetitive, nested-loop - based targeted application source code programs.

Modeling and simulation in a formal design framework

In this paper, a formal design framework is described that it allows for correct-by-construction complex circuit generation from high-level program models with arbitrary data and control flow. The formal nature of the program compilation allows for design flow iteration -- free design, rapid development times and bug-free product implementation. The discussed formal framework, translates program subroutines into hardware coprocessors. The translation process is implemented with formal compiler-compiler and logic programming techniques. Due to this the functionality of the generated finite-state-machines and datapaths is formally equivalent to that of the source programs. This is practically proven in this paper with verification of the designed systems at both the program code and at the produced circuit RTL simulations level. The presented design flow enables rapid prototyping and it allows for compression of the development time from months down to a few hours.

Synthesis of customised hardware from ADA

Tools which permit the synthesis of hardware from high-level specifications are vital for reliable design on an acceptable timescale, and are opening up exciting possibilities in the use of custom coprocessors, rapid prototyping and the design of flexible mixed hardware-software systems. We are exploring a method for the translation of standard ADA code into hardware, by compiling ADA into a standard HDL format which can be synthesised by existing commercial packages. This paper sets out our approach of using an Intermediate Table Format (ITF) for high-level transformations and compilation into synthesisable HDL code.<<ETX>>

Loop pipelining in high-level synthesis with CCC

High-level synthesis allows the use of high-level programming languages for hardware design. Traditional programming with the C and ADA languages can lead to efficient hardware description through recently developed high-level synthesis tools. Compilers play an important role in this process, since they can bridge differences between software programming and hardware design methodologies, thus making high-level synthesis tools better accepted by the scientific community. Furthermore, modern compiler optimizations can be employed in order to obtain optimal hardware descriptions. Loop transformations are often the focus of compiler optimizations, since they can result in significant performance improvement, for both software and hardware programming. In this paper, we discuss the implementation of loop pipelining in the front-end compiler of the CCC high-level synthesis tool, and in particular we present new optimization techniques that lead to a decreased number of states in the FSM-based output of CCC. We present several experiments conducted on the Livermore loops and the MPEG2 open-source code, which prove the claimed improvement.

Source-Level Compiler Optimizations for High-Level Synthesis

With high-level synthesis becoming the preferred method for hardware design, tools that operate on high-level programming languages and optimize hardware output are crucial for successful synthesis. In high-level synthesis, conventional programming language codes describe hardware behavior. Those codes are translated into RTL-level description by some appropriate tool. Common such tools that not only translate, but also optimize code, are programming language compilers. Compilers can make the transition from software to hardware smooth, allowing programmers to use their software skills on hardware programming, without any language compromises. Nonetheless, compilers also utilize optimization techniques to obtain a better output hardware description. In this paper, we discuss compiler issues for high-level synthesis, and present the results of several compiler transformations that can be implemented on our C language compiler front end of the CCC high-level synthesis tool. The results are taken from experiments conducted on the MPEG2 open-source codes, and prove the importance of such transformations in high-level synthesis.

Performance and power simulation of a functional-unit-network processor with simplescalar and wattch

Loop acceleration is a means to enhance performance of a single- or multiple-issue microprocessor core. A new edge-like processor architecture incorporates a loop accelerator directly in the out-of-order back end of the processor, forming an extended hypercube interconnected network of functional unit nodes. In this work, we have simulated a full processor pipeline of our architecture in a high-level language. In particular, we have extended the Simplescalar, a well-known processor simulator, to include our multifunctional-unit back-end design, and to support our special instructions for loop acceleration. Thus, instructions forming qualified loops are scheduled and dispatched only once for execution, remaining in the back end for all loop iterations, interchanging values in a data-flow fashion. We have also utilized the Wattch power estimation tool, which has been traditionally coupling Simplescalar to produce an estimation of power consumption during simulation, to show that our design results in significant power savings. Since loop instructions reside in the functional unit nodes during loop execution, all front end of the pipeline is turned off and the register file and the instruction cache are kept at low power at that time. Experiments conducted include simulating execution of small loop-based benchmarks from the Livermore loops, as well as longer real-life code taken from open-source mpeg video compression codes. All experiments exhibit the expected performance and power consumption improvements, verifying earlier performance measurements on the HDL model of the back end.

Formal Design Flows for Embedded IoT Hardware

Taking into account the current complexity of IoT devices and hardware/software modules, there is a need to shorten the design time of embedded systems along with their custom hardware blocks. Already many microcontroller vendors include embedded hardware security blocks into their products so as to prohibit the potential security attackers and threats. Moreover, when the hardware design tools and methods are based on formal and rapid techniques, then product-to-market delays are eliminated. This chapter discusses a novel high-level synthesis technique which is rapid, and is based on formal methodologies. This synthesis-based methodology is used for the rapid and formal development of custom hardware blocks that collaborate with their host environment to deliver complete IoT nodes. Due to the formal nature of the logic programming-based synthesis transformations of the design tools, the produced hardware is provably correct in respect with the given executable specifications in high-level program code. Moreover, the automatically generated verification testbenches from exactly the same synthesis design model make the verification unified, formal, and rapid. The discussed synthesis and verification approach is rapid, flexible, formal and includes a number of input and output language format making it suitable to plug into any of the industrial design flows. A number of design experiments prove the usability of the discussed design flow.

Minimal-area loop pipelining for high-level synthesis with CCC

Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless, compiler optimizations can improve efficiency of automatically generated hardware descriptions and make high-level synthesis to become the dominant technology to build more complicated hardware as well. Compilers, well known and explored software tools, can allow programmers to use their software skills on hardware programming, without any language compromises. Furthermore, compiler optimizations transform the input code, in order to produce a high-quality high-performance output hardware description. In this paper, we discuss compiler issues for high-level synthesis, and in particular, the incorporation of loop pipelining in the C language front end of the CCC high-level synthesis tool. We also present a novel pipelining technique that minimizes the area used for the pipeline prologue and epilogue. Results from experiments on the Livermore loops and Mpeg2 open-source codes validate our technique.

Compiler transformations in hardware synthesis of Mpeg2 codes

High-level synthesis is the technique that translates high-level programming language programs into equivalent hardware descriptions. The use of conventional programming languages as input to high-level synthesis is challenging, due to the conceptual differences between software programs and hardware descriptions, but is nonetheless becoming the preferred input to high-level synthesis tools. Compilers play an important role in this process, since they can not only bridge such differences, thus making high-level synthesis tools better accepted by the scientific community, but they can also apply code transformations that target an optimized hardware output. In this paper, we discuss a number of transformations that can be implemented in the C language front end of the CCC high-level synthesis tool. We present experiments of such transformations conducted on the MPEG2 open-source code, which prove that compiler optimizations can have a significant positive impact in high-level synthesis tools.

High-level Synthesis-based signal coding

The extremely populated state of current ICs have motivated for advanced High-level Synthesis techniques to be used for specialized circuits. Due to the complexity and lack of flexibility of existing High-level Synthesis tools, most of the low level circuits such as signal coding blocks were left out of the EDA scope and to the responsibility of layout engineers. In this paper we present a High-level Synthesis approach which is suitable for both complex and low level custom block design. The advantage of this approach is a uniform and formal treatment of both high-level and low-level design, as well as provably correct results.